[coreboot-gerrit] New patch to review for coreboot: 3a94033 pistachio: increase the size of romstage to 36K

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9589

-gerrit

commit 3a94033d9adb32c6a9ff4c475286cfa6cc987298
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Mon Dec 8 12:51:09 2014 +0000

    pistachio: increase the size of romstage to 36K
    
    This is necessary for the subsequent changes that will add to the size
    of romstage.
    
    BUG=chrome-os-partner:31438
    TEST=coreboot builds successfully;tested on Pistachio FPGA
    BRANCH=none
    
    Change-Id: I132215bd44708913d878bbd8b6147bef535b52df
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 00f73f9d80a36fc43735f093365564b9d74ed7f7
    Original-Change-Id: Ie858416a1c9ab63cfe85eea40a76a093cbd2c79c
    Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/233871
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Original-Commit-Queue: Vadim Bendebury <vbendeb at chromium.org>
    Original-Tested-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 554ebfc..1c7ea9a 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -29,7 +29,7 @@ SECTIONS
 	/* GRAM becomes the SRAM. */
 	SRAM_START(0x9a000000)
 	BOOTBLOCK(0x9a000000, 16K)
-	ROMSTAGE(0x9a004000, 32K)
+	ROMSTAGE(0x9a004000, 36K)
 	STACK(0x9a01c000, 8K)
 	PRERAM_CBMEM_CONSOLE(0x9a01e000, 8K)
 	SRAM_END(0x9a020000)