[coreboot-gerrit] New patch to review for coreboot: ac6d64c arch: armv7: Fix cache sync instructions.

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9587

-gerrit

commit ac6d64c1f3e81679505239df1cbc2ab8db954c75
Author: Deepa Dinamani <deepad at codeaurora.org>
Date:   Wed Dec 17 13:40:43 2014 -0800

    arch: armv7: Fix cache sync instructions.
    
    When the i-cache is on and the d-cache is off, the L1 i-cache is still
    fetching information through L2 cache.
    Since L2 cache is never invalidated, it has stale information.
    
    BRANCH=storm
    BUG=none
    TEST=Resolves the invalidate data fetch from i-cache while jumping from
    bootblock to romstage.
    
    Change-Id: Ibaca1219be2e40ce5bbbd1c124863d0ea71d0466
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: a13e20f9b242d8193dcb314a2bdc708c6bdfea51
    Original-Change-Id: I252682d372bd505f525f075461b327e4bcf70a1a
    Original-Signed-off-by: Deepa Dinamani <deepad at codeaurora.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/236422
    Original-Reviewed-by: Trevor Bourget <tbourget at codeaurora.org>
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Commit-Queue: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/arm/armv7/cache.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c
index 31819f7..1f762b8 100644
--- a/src/arch/arm/armv7/cache.c
+++ b/src/arch/arm/armv7/cache.c
@@ -142,7 +142,15 @@ void dcache_mmu_enable(void)
 
 void cache_sync_instructions(void)
 {
-	dcache_clean_all();	/* includes trailing DSB (in assembly) */
+	uint32_t sctlr;
+
+	sctlr = read_sctlr();
+
+	if (sctlr & SCTLR_C)
+		dcache_clean_all();
+	else if (sctlr & SCTLR_I)
+		dcache_clean_invalidate_all();
+
 	iciallu();		/* includes BPIALLU (architecturally) */
 	dsb();
 	isb();