[coreboot-gerrit] Patch merged into coreboot/master: f059b24 broadwell: Add function to apply PRR to a range of SPI flash

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit f059b241ad1ebd6b2084578b9284a19d018e8800
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Jan 15 15:42:43 2015 -0800

    broadwell: Add function to apply PRR to a range of SPI flash
    
    This function will use the next available/free protected range
    register to cover the specified region of flash and write
    protect it until the next reset.
    
    This will be used by the common MRC cache code to protect the
    RW_MRC_CACHE region after it is updated.
    
    In order to communicate to the common NVM code that this function
    is defined also enable CONFIG_MRC_SETTINGS_PROTECT variable.
    
    BUG=chrome-os-partner:28234
    BRANCH=broadwell
    TEST=build and boot on samus
    
    Change-Id: I710c6a69f725479411ed978cc615e1bb78fb42b8
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 25365433be0f190e10a96d9946b8ea90c883b78a
    Original-Change-Id: I4a4cd27f9f4a94b9134dcba623f33b114299818f
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/241129
    Original-Reviewed-by: Shawn N <shawnn at chromium.org>
    Reviewed-on: http://review.coreboot.org/9493
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/9493 for details.

-gerrit