[coreboot-gerrit] Patch merged into coreboot/master: cad2b7b broadwell: Skip steps when disabling PCIe port

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit cad2b7b6e896ffd11d09f0017da1fd1f80d61c09
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Jan 14 17:30:20 2015 -0800

    broadwell: Skip steps when disabling PCIe port
    
    When disabling PCIe ports skip steps if no card is detected.
    This prevents the loop from timing out on each empty slot.
    
    BUG=chrome-os-partner:31424
    BRANCH=broadwell
    TEST=build and boot on samus, check that this code is
    no longer timing out when disabling PCIe ports
    
    Change-Id: I84ee0e0e325784b3af06abe70420c07cf6e13ed2
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 4d759e2350dd00ceb7df196ac7008729dc1e4cef
    Original-Change-Id: Idd88f0f1191a5465a0d8dcca07b5c3a5c5ca8855
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/240851
    Original-Reviewed-by: Wenkai Du <wenkai.du at intel.com>
    Original-Reviewed-by: Shawn N <shawnn at chromium.org>
    Reviewed-on: http://review.coreboot.org/9489
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/9489 for details.

-gerrit