[coreboot-gerrit] Patch merged into coreboot/master: e0dae99 PCI - Add interrupt disable bit definition

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit e0dae99b47faf6e750938bc52550128a4351f93e
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Thu Jan 15 15:02:55 2015 -0800

    PCI - Add interrupt disable bit definition
    
    BRANCH=none
    BUG=None
    TEST=Build Braswell/Strago
    
    Change-Id: I11a4c02af3b40edf2252b9e20298941b99f31d21
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 1629d7454a3d4adb8930d14849c41c9a711f4c9a
    Original-Change-Id: Ie907637f7c823de681ef2e315e803dffc6ad33d3
    Original-Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/241081
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/9487
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/9487 for details.

-gerrit