[coreboot-gerrit] Patch merged into coreboot/master: dd281ed tpm: Add ramstage driver and interrupt configuration

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit dd281edcfab464c4bf9df3fa9d86db5639c845e0
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Oct 30 15:20:19 2014 -0700

    tpm: Add ramstage driver and interrupt configuration
    
    This adds a ramstage driver for the TPM and allows the interrupt
    to be configured in devicetree.cb.
    
    The interrupt vector is set like other PNP devices, and the
    interrupt polarity is set with a register configuration variable.
    
    These values are written into locality 0 TPM_INT_VECTOR and
    TPM_INT_ENABLE and then all interrupts are disabled so they are
    not used in firmware but can be enabled by the OS.
    
    It also adds an ACPI device for the TPM which will configure the
    reported interrupt based on what has been written into the TPM
    during ramstage.  The _STA method returns enabled if CONFIG_LPC_TPM
    is enabled, and the _CRS method will only report an interrupt if one
    has been set in the TPM itself.
    
    The TPM memory address is added by the driver and declared in the
    ACPI code.  In order to access it in ACPI a Kconfig entry is added for
    the default TPM TIS 1.2 base address.  Note that IO address 0x2e is
    required to be declared in ACPI for the kernel driver to probe correctly.
    
    BUG=chrome-os-partner:33385
    BRANCH=samus,auron
    TEST=manual testing on samus:
    1) Add TPM device in devicetree.cb with configured interrupt and
    ensure that it is functional in the OS.
    2) Test with active high and active low, edge triggered and level
    triggered setups.
    3) Ensure that with no device added to devicetree.cb that the TPM
    is still functional in polling mode.
    
    Change-Id: Iee2a1832394dfe32f3ea3700753b8ecc443c7fbf
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: fc2c106caae939467fb07f3a0207adee71dda48e
    Original-Change-Id: Id8a5a251f193c71ab2209f85fb470120a3b6a80d
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/226661
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/9469
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/9469 for details.

-gerrit