[coreboot-gerrit] Patch merged into coreboot/master: 9afc5c0 baytrail: Switch from ACPI mode to PCI mode for legacy support

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 9afc5c05f083631424e4e6a86a6c08fcc3e6473b
Author: Marc Jones <marc.jones at se-eng.com>
Date:   Wed Sep 24 10:53:48 2014 -0600

    baytrail: Switch from ACPI mode to PCI mode for legacy support
    
    Most Baytrail based devices MMIO registers are reported in ACPI
    space and the device's PCI config space is disabled. The PCI config
    space is required for many "legacy" OSs that don't have the ACPI
    driver loading mechanism. Depthcharge signals the legacy boot
    path via the SMI 0xCC and the coreboot SMI handler can switch the
    device specific registers to re-enable PCI config space.
    
    BUG=chrome-os-partner:30836
    BRANCH=None
    TEST=Build and boot Rambi SeaBIOS.
    
    Change-Id: I87248936e2a7e026f38c147bdf0df378e605e370
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: dbb9205ee22ffce44e965be51ae0bc62d4ca5dd4
    Original-Change-Id: Ia5e54f4330eda10a01ce3de5aa4d86779d6e1bf9
    Original-Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/219801
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Mike Loptien <mike.loptien at se-eng.com>
    Original-Tested-by: Mike Loptien <mike.loptien at se-eng.com>
    Reviewed-on: http://review.coreboot.org/9459
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/9459 for details.

-gerrit