[coreboot-gerrit] New patch to review for coreboot: 187144b tegra132: Make non-vboot2 memlayout more useful

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9536

-gerrit

commit 187144bb555f71c85f06e2405604798d1fbfcc65
Author: Furquan Shaikh <furquan at google.com>
Date:   Fri Nov 21 17:07:16 2014 -0800

    tegra132: Make non-vboot2 memlayout more useful
    
    Update non-vboot2 memlayout:
    1) Add timestamp region
    2) Increase ramstage size
    3) Change name from memlayout_vboot.ld to memlayout.ld so that any non-vboot
    upstream board can also use this layout.
    
    BUG=None
    BRANCH=None
    TEST=Compiles and boots to kernel prompt on ryu with vboot selected instead of
    vboot2.
    
    Change-Id: Idced98f9df7cdbab5f62cd1e382c6046ade1d867
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 20fffa282b20fb32ce2ff687f4479be630f90fcf
    Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
    Original-Change-Id: I91accd54efc53ab563a2063b9c6e9390f5dd527f
    Original-Reviewed-on: https://chromium-review.googlesource.com/231547
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
---
 src/mainboard/google/rush/memlayout.ld             |  2 +-
 src/mainboard/google/rush_ryu/memlayout.ld         |  2 +-
 src/soc/nvidia/tegra132/include/soc/memlayout.ld   | 44 ++++++++++++++++++++++
 .../nvidia/tegra132/include/soc/memlayout_vboot.ld | 43 ---------------------
 4 files changed, 46 insertions(+), 45 deletions(-)

diff --git a/src/mainboard/google/rush/memlayout.ld b/src/mainboard/google/rush/memlayout.ld
index 5bd72e5..d8fdb9a 100644
--- a/src/mainboard/google/rush/memlayout.ld
+++ b/src/mainboard/google/rush/memlayout.ld
@@ -1,5 +1,5 @@
 #if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
 #include <soc/memlayout_vboot2.ld>
 #else
-#include <soc/memlayout_vboot.ld>
+#include <soc/memlayout.ld>
 #endif
diff --git a/src/mainboard/google/rush_ryu/memlayout.ld b/src/mainboard/google/rush_ryu/memlayout.ld
index 5bd72e5..d8fdb9a 100644
--- a/src/mainboard/google/rush_ryu/memlayout.ld
+++ b/src/mainboard/google/rush_ryu/memlayout.ld
@@ -1,5 +1,5 @@
 #if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
 #include <soc/memlayout_vboot2.ld>
 #else
-#include <soc/memlayout_vboot.ld>
+#include <soc/memlayout.ld>
 #endif
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout.ld b/src/soc/nvidia/tegra132/include/soc/memlayout.ld
new file mode 100644
index 0000000..a7e3635
--- /dev/null
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout.ld
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+/*
+ * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
+ * so the bootblock loading address must be placed after that. After the
+ * handoff that area may be reclaimed for other uses, e.g. CBFS cache.
+ * TODO: Did this change on Tegra132? What's the new valid range?
+ */
+
+SECTIONS
+{
+	SRAM_START(0x40000000)
+	PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
+	PRERAM_CBFS_CACHE(0x40002000, 84K)
+	STACK(0x40017000, 16K)
+	BOOTBLOCK(0x4001B800, 22K)
+	ROMSTAGE(0x40021000, 124K)
+	SRAM_END(0x40040000)
+
+	DRAM_START(0x80000000)
+	POSTRAM_CBFS_CACHE(0x80100000, 1M)
+	RAMSTAGE(0x80200000, 256K)
+}
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld
deleted file mode 100644
index c097c3c..0000000
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-/*
- * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
- * so the bootblock loading address must be placed after that. After the
- * handoff that area may be reclaimed for other uses, e.g. CBFS cache.
- * TODO: Did this change on Tegra132? What's the new valid range?
- */
-
-SECTIONS
-{
-	SRAM_START(0x40000000)
-	PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
-	CBFS_CACHE(0x40002000, 88K)
-	STACK(0x40018000, 16K)
-	BOOTBLOCK(0x4001C000, 20K)
-	ROMSTAGE(0x40021000, 124K)
-	SRAM_END(0x40040000)
-
-	DRAM_START(0x80000000)
-	RAMSTAGE(0x80200000, 192K)
-}