[coreboot-gerrit] New patch to review for coreboot: 8e6f2ce tegra132: Increase space for romstage in memlayout

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9512

-gerrit

commit 8e6f2ce2853674158cc0639feeec567c7e7710a5
Author: Furquan Shaikh <furquan at google.com>
Date:   Mon Nov 10 22:35:04 2014 -0800

    tegra132: Increase space for romstage in memlayout
    
    Stack and Timestamp need lesser than 2K and since romstage is running out of
    memory, adjust the overall memory assignment.
    
    BUG=chrome-os-partner:33676
    BRANCH=None
    TEST=Compiles and boots to kernel prompt.
    
    Change-Id: I5076252ae87268bd4e964c282d1cc337e0ea4e70
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: f2d5d29e6f0f5058a41ed30aae98f79574e31609
    Original-Change-Id: I0134f25dd49f2940bb159d131aaee12f81e13ef7
    Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/229001
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Tom Warren <twarren at nvidia.com>
    Original-Commit-Queue: Tom Warren <twarren at nvidia.com>
---
 src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index 1709392..c75bdc0 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -35,10 +35,10 @@ SECTIONS
 	PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
 	CBFS_CACHE(0x40002000, 72K)
 	VBOOT2_WORK(0x40014000, 16K)
-	STACK(0x40018000, 8K)
-	BOOTBLOCK(0x4001A000, 20K)
-	VERSTAGE(0x4001F000, 60K)
-	ROMSTAGE(0x4002E000, 72K)
+	STACK(0x40018000, 2K)
+	BOOTBLOCK(0x40019000, 20K)
+	VERSTAGE(0x4001E000, 60K)
+	ROMSTAGE(0x4002D000, 76K)
 	SRAM_END(0x40040000)
 
 	DRAM_START(0x80000000)