[coreboot-gerrit] Patch set updated for coreboot: 31423bf Intel SOC Common: Reset

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9505

-gerrit

commit 31423bfb04e82bee648b6f1349f5bde87bf221b0
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Mon Feb 9 21:16:14 2015 -0800

    Intel SOC Common: Reset
    
    Move reset support into the Intel common branch.  Prevent breaking of
    existing platforms by using a Kconfig value to select use of the common
    reset code.
    
    BRANCH=none
    BUG=None
    TEST=Build and run on Glados
    
    Change-Id: I5ba86ef585dde3ef4ecdcc198ab615b5c056d985
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 85d8a6d9628a66cc8d73176d460cd6c5bf6bd6b2
    Original-Change-Id: I5048ccf3eb593d59301ad8e808c4e281b9a0aa98
    Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/248301
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy at intel.com>
    Original-Tested-by: Leroy P Leahy <leroy.p.leahy at intel.com>
---
 src/soc/intel/common/Kconfig      |  4 +++
 src/soc/intel/common/Makefile.inc |  2 ++
 src/soc/intel/common/reset.c      | 54 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 60 insertions(+)

diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 8b02a4a..70f3e01 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -17,3 +17,7 @@ config MRC_SETTINGS_CACHE_SIZE
 endif # CACHE_MRC_SETTINGS
 
 endif # HAVE_MRC
+
+config COMMON_RESET
+	bool
+	default n
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 0c39d80..1861ec3 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -2,3 +2,5 @@ ramstage-y += hda_verb.c
 ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
 ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
 romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
+ramstage-$(CONFIG_COMMON_RESET) += reset.c
+romstage-$(CONFIG_COMMON_RESET) += reset.c
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
new file mode 100644
index 0000000..2046c3b
--- /dev/null
+++ b/src/soc/intel/common/reset.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <reset.h>
+
+/* Reset control port */
+#define RST_CNT			0xcf9
+#define FULL_RST		(1 << 3)
+#define RST_CPU			(1 << 2)
+#define SYS_RST			(1 << 1)
+
+void hard_reset(void)
+{
+	/* S0->S5->S0 trip. */
+	outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
+	while (1)
+		hlt();
+}
+
+void soft_reset(void)
+{
+	/* PMC_PLTRST# asserted. */
+	outb(RST_CPU | SYS_RST, RST_CNT);
+	while (1)
+		hlt();
+}
+
+void cpu_reset(void)
+{
+	/* Sends INIT# to CPU */
+	outb(RST_CPU, RST_CNT);
+	while (1)
+		hlt();
+}