[coreboot-gerrit] Patch set updated for coreboot: ce71ab3 broadwell: Work around VBIOS framebuffer issue

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Fri Apr 10 03:26:10 CEST 2015


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9464

-gerrit

commit ce71ab338ccb1bdf534dc6aed9dad864b6ded93d
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Oct 9 16:13:24 2014 -0700

    broadwell: Work around VBIOS framebuffer issue
    
    The first 64 bytes of the framebuffer contain garbage after running
    the option rom and after calling the VBE mode set with the flag to
    clear the framebuffer.
    
    Work around this issue by clearing the first 64 bytes in the framebuffer
    in the broadwell graphics setup code after it executes the VBIOS.
    
    BUG=chrome-os-partner:32771
    BRANCH=samus,auron
    TEST=build and boot on samus in dev mode, check for graphical corruption
    
    Change-Id: I0381e32a5ea17e13c4ed598835999c12136418cf
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: f29c1b0b7c100cf290f82de671042823032f71c9
    Original-Change-Id: I072bc913f7daea16e4861a7549e1b4ec85cde4cd
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/222676
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/broadwell/igd.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index d8b51a3..41a6961 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -523,6 +523,15 @@ static void igd_init(struct device *dev)
 		reg_script_run_on_dev(dev, haswell_late_init_script);
 	}
 
+	if (gfx_get_init_done()) {
+		/*
+		 * Work around VBIOS issue that is not clearing first 64
+		 * bytes of the framebuffer during VBE mode set.
+		 */
+		struct resource *fb = find_resource(dev, PCI_BASE_ADDRESS_2);
+		memset((void *)((u32)fb->base), 0, 64);
+	}
+
 	if (!gfx_get_init_done() && acpi_slp_type != 3) {
 		/*
 		 * Enable DDI-A if the Option ROM did not execute:



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