[coreboot-gerrit] Patch set updated for coreboot: 5c4cf57 PCI - Add interrupt disable bit definition

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9487

-gerrit

commit 5c4cf5746b857cad08e0942be94caed304ec4be6
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Thu Jan 15 15:02:55 2015 -0800

    PCI - Add interrupt disable bit definition
    
    BRANCH=none
    BUG=None
    TEST=Build Braswell/Strago
    
    Change-Id: I11a4c02af3b40edf2252b9e20298941b99f31d21
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 1629d7454a3d4adb8930d14849c41c9a711f4c9a
    Original-Change-Id: Ie907637f7c823de681ef2e315e803dffc6ad33d3
    Original-Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/241081
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/include/device/pci_def.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index c49e4eb..ef3427b 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -18,6 +18,7 @@
 #define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */
 #define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
 #define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
+#define  PCI_COMMAND_INT_DISABLE 0x400	/* Interrupt disable */
 
 #define PCI_STATUS		0x06	/* 16 bits */
 #define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */