[coreboot-gerrit] Patch set updated for coreboot: 88d2e4c broadwell: Correct XHCI offset for USB 3.0 ports

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9502

-gerrit

commit 88d2e4cbfc77ce20b4c333091bd846962923979d
Author: Julius Werner <jwerner at chromium.org>
Date:   Fri Feb 6 15:34:14 2015 -0800

    broadwell: Correct XHCI offset for USB 3.0 ports
    
    Looks like Intel has added two more USB 2.0 ports from LynxPoint to
    Broadwell, which shifted the port offsets of the USB 3.0 ports behind
    them. The USB 2.0 ports are now 0x480 to 0x520 and the 3.0 ones 0x530 to
    0x560 (at least according to what my kernel seems to think). The offset
    of the first USB 3.0 port is hardcoded and seems to have been copied
    over without accounting for this, meaning when we try to operate on all
    USB 3.0 ports we actually operate on the last two 2.0 and the first two
    3.0 ports instead.
    
    This patch should fix the bug for now. In the future, we might want to
    consider dynamically detecting port locations through the Protocol
    Capability structures at the end of the XHCI register set instead.
    
    BRANCH=samus
    BUG=chrome-os-partner:35320
    TEST=TODO
    
    Change-Id: Ifab6e484980fd4cd0daf80ceb292ddced2ab1aea
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 525f359c0b6b95b260add2b4617fd86119d69397
    Original-Change-Id: Ic2becf2b043612270909ceef66e7d58efc8fcbe1
    Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/247351
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-by: Todd Broch <tbroch at chromium.org>
---
 src/soc/intel/broadwell/include/soc/xhci.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h
index 3f4fb4e..2b899a3 100644
--- a/src/soc/intel/broadwell/include/soc/xhci.h
+++ b/src/soc/intel/broadwell/include/soc/xhci.h
@@ -39,7 +39,7 @@
 #define XHCI_USB3PDO		0xe8
 
 /* XHCI Memory Registers */
-#define XHCI_USB3_PORTSC(port)	(0x510 + (port * 0x10))
+#define XHCI_USB3_PORTSC(port)	(0x530 + (port * 0x10))
 #define  XHCI_USB3_PORTSC_CHST	(0x7f << 17)
 #define  XHCI_USB3_PORTSC_WCE	(1 << 25)	/* Wake on Connect */
 #define  XHCI_USB3_PORTSC_WDE	(1 << 26)	/* Wake on Disconnect */