[coreboot-gerrit] New patch to review for coreboot: 4c18acb broadwell: Add configuration for tuning VR for C-state operations

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9497

-gerrit

commit 4c18acbd967da972ee5aba889edafd7e2714ea3d
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Jan 20 07:53:27 2015 -0800

    broadwell: Add configuration for tuning VR for C-state operations
    
    Add some configuration options that allow tuning the VR for C-state
    settings that may be able to reduce noise.
    
    - Add option to enable slow VR ramp rate for C-state exit
    - Add variable to configure the minimum C6/C7 voltage
    
    BUG=chrome-os-partner:34771
    BRANCH=broadwell
    TEST=build and boot on samus
    
    Change-Id: I01445d62fbfcf200b787b924d8d72685819a4715
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: ed8f355e60292c82791817ae31bff58ac2390a72
    Original-Change-Id: I8af75b69c8b55d3e210170ee96f8e22c2fd76374
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/241950
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/broadwell/chip.h | 22 ++++++++++++++++++++++
 src/soc/intel/broadwell/cpu.c  | 20 ++++++++++++++++----
 2 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index 703c865..77c517d 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -130,6 +130,28 @@ struct soc_intel_broadwell_config {
 	/* Enable S0iX support */
 	int s0ix_enable;
 
+	/*
+	 * Minimum voltage for C6/C7 state:
+	 * 0x67 = 1.6V (full swing)
+	 *  ...
+	 * 0x79 = 1.7V
+	 *  ...
+	 * 0x83 = 1.8V (no swing)
+	 */
+	int vr_cpu_min_vid;
+
+	/*
+	 * Set slow VR ramp rate on C-state exit:
+	 * 0 = Fast VR ramp rate / 2
+	 * 1 = Fast VR ramp rate / 4
+	 * 2 = Fast VR ramp rate / 8
+	 * 3 = Fast VR ramp rate / 16
+	 */
+	int vr_slow_ramp_rate_set;
+
+	/* Enable slow VR ramp rate */
+	int vr_slow_ramp_rate_enable;
+
 	/* Deep SX enable */
 	int deep_sx_enable_ac;
 	int deep_sx_enable_dc;
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index b227e0d..9073241 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -180,6 +180,8 @@ static u32 pcode_mailbox_read(u32 command)
 
 static void initialize_vr_config(void)
 {
+	device_t dev = SA_DEV_ROOT;
+	config_t *conf = dev->chip_info;
 	msr_t msr;
 
 	printk(BIOS_DEBUG, "Initializing VR config.\n");
@@ -203,17 +205,27 @@ static void initialize_vr_config(void)
 	msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
 	/* Set IOUT_OFFSET to 0. */
 	msr.hi &= ~0xff;
-	/* Set exit ramp rate to fast. */
-	msr.hi |= (1 << (50 - 32));
 	/* Set entry ramp rate to slow. */
 	msr.hi &= ~(1 << (51 - 32));
 	/* Enable decay mode on C-state entry. */
 	msr.hi |= (1 << (52 - 32));
-	/* Set the slow ramp rate to be fast ramp rate / 4 */
+	/* Set the slow ramp rate */
 	msr.hi &= ~(0x3 << (53 - 32));
-	msr.hi |= (0x01 << (53 - 32));
+	/* Configure the C-state exit ramp rate. */
+	if (conf->vr_slow_ramp_rate_enable) {
+		/* Configured slow ramp rate. */
+		msr.hi |= ((conf->vr_slow_ramp_rate_set & 0x3) << (53 - 32));
+		/* Set exit ramp rate to slow. */
+		msr.hi &= ~(1 << (50 - 32));
+	} else {
+		/* Fast ramp rate / 4. */
+		msr.hi |= (0x01 << (53 - 32));
+		/* Set exit ramp rate to fast. */
+		msr.hi |= (1 << (50 - 32));
+	}
 	/* Set MIN_VID (31:24) to allow CPU to have full control. */
 	msr.lo &= ~0xff000000;
+	msr.lo |= (conf->vr_cpu_min_vid & 0xff) << 24;
 	wrmsr(MSR_VR_MISC_CONFIG, msr);
 
 	/*  Configure VR_MISC_CONFIG2 MSR. */