[coreboot-gerrit] New patch to review for coreboot: 028eed1 samus: Add ACPI binding for rt5677 codec SPI

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9486

-gerrit

commit 028eed16cf668c63cee26eb2b1343330c6dd6f27
Author: Ben Zhang <benzh at chromium.org>
Date:   Mon Dec 15 17:38:11 2014 -0800

    samus: Add ACPI binding for rt5677 codec SPI
    
    We'll need to find a real ACPI device ID for
    the rt5677 SPI driver. "RT5677AA" is temporary.
    
    BUG=chrome-os-partner:33495
    BRANCH=samus
    TEST=load firmware via SPI; hotword detection works
    
    Change-Id: I6dc55c4641c27a38570debe841a6afeb048eb868
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: f0d7013b62c78deb82db1a431f079c79eded5270
    Original-Change-Id: Ifb4a1b12776669e21c0b7c4679246717d72981ad
    Original-Signed-off-by: Ben Zhang <benzh at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/235902
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/mainboard/google/samus/acpi/mainboard.asl | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
index 1138f43..54a46d5 100644
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ b/src/mainboard/google/samus/acpi/mainboard.asl
@@ -353,3 +353,29 @@ Scope (\_SB.PCI0.I2C1)
 		}
 	}
 }
+
+Scope (\_SB.PCI0.SPI0)
+{
+	Device (CODC)
+	{
+		// TODO: Need official HID.
+		Name (_HID, "RT5677AA")
+		Name (_UID, 1)
+		Name (_CRS, ResourceTemplate ()
+		{
+			SpiSerialBus (
+				0,                   // DeviceSelection (CS0?)
+				PolarityLow,         // DeviceSelectionPolarity
+				FourWireMode,        // WireMode
+				8,                   // DataBitLength
+				ControllerInitiated, // SlaveMode
+				1000000,             // ConnectionSpeed (1MHz)
+				ClockPolarityLow,    // ClockPolarity
+				ClockPhaseFirst,     // ClockPhase
+				"\\_SB.PCI0.SPI0",   // ResourceSource
+				0,                   // ResourceSourceIndex
+				ResourceConsumer,    // ResourceUsage
+			)
+		})
+	}
+}