[coreboot-gerrit] Patch merged into coreboot/master: e32b6e7 libpayload: PCI bus scan - Eliminate endless loop

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit e32b6e71967c4a8deaa31955dc49009631d1f495
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Wed Dec 17 13:05:26 2014 -0800

    libpayload: PCI bus scan - Eliminate endless loop
    
    Don't attempt to scan the PCI bus if the bridge is disabled.  When
    the PCI bridge is not setup and enabled, it is possible for the
    secondary bus register to contain the value zero (0).  In this case
    the usb_scan_pci_bus routine gets into an infinite recursive loop
    which ends only when the heap or stack is exhausted.  This patch
    verifies that the PCI bridge is enabled by verifying that it is
    enabled for either memory or I/O operations.  When enabled, the
    secondary bus is scanned.
    
    BRANCH=none
    BUG=None
    TEST=Build and run on Samus
    
    Change-Id: I6826dc1d73b7c24729de5ac7c4d3534922ca73c5
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 63d04b47934761351b54c847a2692bdef81ce54f
    Original-Change-Id: I855240c52fa3eba841e6754816ebbcb824abc4cd
    Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/236382
    Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy at intel.com>
    Original-Tested-by: Leroy P Leahy <leroy.p.leahy at intel.com>
    Original-Reviewed-by: Giri P Mudusuru <giri.p.mudusuru at intel.com>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/8734
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/8734 for details.

-gerrit