[coreboot-gerrit] New patch to review for coreboot: 3946eef mainboard/lenovo/t430s, t530, x230:enable usb3, set xhci overcurrent mapping

[Nicolas Reinecke (nr@das-labor.org)]

Nicolas Reinecke (nr at das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9451

-gerrit

commit 3946eeff25cb376f5451321a67711eafa01b93e1
Author: Nicolas Reinecke <nr at das-labor.org>
Date:   Tue Mar 31 01:40:46 2015 +0200

    mainboard/lenovo/t430s,t530,x230:enable usb3, set xhci overcurrent mapping
    
    Tested on T530, T430s.
    Verified with lspci dump.
    
    Change-Id: I45acadb0c55534a67f7ad3e7bd84f4482a4344d7
    Signed-off-by: Nicolas Reinecke <nr at das-labor.org>
---
 src/mainboard/lenovo/t430s/devicetree.cb | 4 ++++
 src/mainboard/lenovo/t530/devicetree.cb  | 4 ++++
 src/mainboard/lenovo/x230/devicetree.cb  | 1 +
 3 files changed, 9 insertions(+)

diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb
index e2ae392..af3de6c 100644
--- a/src/mainboard/lenovo/t430s/devicetree.cb
+++ b/src/mainboard/lenovo/t430s/devicetree.cb
@@ -67,6 +67,10 @@ chip northbridge/intel/sandybridge
 
 			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
 
+			register "xhci_switchable_ports" = "0xf"
+			register "superspeed_capable_ports" = "0xf"
+			register "xhci_overcurrent_mapping" = "0x4000201"
+
 			# Enable zero-based linear PCIe root port functions
 			register "pcie_port_coalesce" = "1"
 			register "c2_latency" = "101"  # c2 not supported
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index 6b769b0..d59524b 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -68,6 +68,10 @@ chip northbridge/intel/sandybridge
 
 			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
 
+			register "xhci_switchable_ports" = "0xf"
+			register "superspeed_capable_ports" = "0xf"
+			register "xhci_overcurrent_mapping" = "0x4000201"
+
 			device pci 14.0 on end # USB 3.0 Controller
 			device pci 16.0 on end # Management Engine Interface 1
 			device pci 16.1 off end # Management Engine Interface 2
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index 08c937f..55677a3 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -69,6 +69,7 @@ chip northbridge/intel/sandybridge
 
 			register "xhci_switchable_ports" = "0xf"
 			register "superspeed_capable_ports" = "0xf"
+			register "xhci_overcurrent_mapping" = "0x4000201"
 
 			# Enable zero-based linear PCIe root port functions
 			register "pcie_port_coalesce" = "1"