[coreboot-gerrit] New patch to review for coreboot: 35681d4 southbrige/intel/bd82x6x: add USB 3.0 overcurrent map config

[Nicolas Reinecke (nr@das-labor.org)]

Nicolas Reinecke (nr at das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9449

-gerrit

commit 35681d4515ef5b385a35b87f48ad1e317375534b
Author: Nicolas Reinecke <nr at das-labor.org>
Date:   Sun Mar 29 17:51:11 2015 +0200

    southbrige/intel/bd82x6x: add USB 3.0 overcurrent map config
    
    Tested on T530.
    
    Change-Id: I9a40e5a1028c7674e6dd54742e6646ba48ce7696
    Signed-off-by: Nicolas Reinecke <nr at das-labor.org>
---
 src/southbridge/intel/bd82x6x/chip.h     | 2 ++
 src/southbridge/intel/bd82x6x/pch.h      | 4 ++++
 src/southbridge/intel/bd82x6x/usb_xhci.c | 8 +++++---
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index f4be82d..f14f4ad 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -94,6 +94,8 @@ struct southbridge_intel_bd82x6x_config {
 	uint32_t xhci_switchable_ports;
 	/* Ports which support SuperSpeed (USB 3.0 additional lanes).  */
 	uint32_t superspeed_capable_ports;
+	/* Overcurrent Mapping for USB 3.0 Ports */
+	uint32_t xhci_overcurrent_mapping;
 };
 
 #endif				/* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 029da9f..8e45f90 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -447,6 +447,10 @@ early_usb_init (const struct southbridge_usb_port *portmap);
 /* USB Overcurrent MAP Register */
 #define USBOCM1		0x35a0	/* 32bit */
 #define USBOCM2		0x35a4	/* 32bit */
+/* XHCI USB 3.0 */
+#define XOCM			0xc0	/* 32bit */
+#define XUSB2PRM		0xd0	/* 32bit */
+#define USB3PRM		0xdc	/* 32bit */
 
 /* ICH7 GPIOBASE */
 #define GPIO_USE_SEL	0x00
diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c
index eb89a7d..767922f 100644
--- a/src/southbridge/intel/bd82x6x/usb_xhci.c
+++ b/src/southbridge/intel/bd82x6x/usb_xhci.c
@@ -33,14 +33,16 @@ static void usb_xhci_init(struct device *dev)
 
 	printk(BIOS_DEBUG, "XHCI: Setting up controller.. ");
 
+	if (config->xhci_overcurrent_mapping)
+		pci_write_config32(dev, XOCM, config->xhci_overcurrent_mapping);
+	pci_write_config32(dev, XUSB2PRM, config->xhci_switchable_ports);
+	pci_write_config32(dev, USB3PRM, config->superspeed_capable_ports);
+
 	/* lock overcurrent map */
 	reg32 = pci_read_config32(dev, 0x44);
 	reg32 |= 1;
 	pci_write_config32(dev, 0x44, reg32);
 
-	pci_write_config32(dev, 0xd4, config->xhci_switchable_ports);
-	pci_write_config32(dev, 0xdc, config->superspeed_capable_ports);
-
 	/* Enable clock gating */
 	reg32 = pci_read_config32(dev, 0x40);
 	reg32 &= ~((1 << 20) | (1 << 21));