[coreboot-gerrit] New patch to review for coreboot: 29e2525 rush: Add vboot2 support

[Aaron Durbin (adurbin@google.com)]

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9432

-gerrit

commit 29e25254b0945dd965b41c8cbbdcca03c8b0dad2
Author: Furquan Shaikh <furquan at google.com>
Date:   Sat Oct 4 17:05:50 2014 -0700

    rush: Add vboot2 support
    
    CQ-DEPEND=CL:221601, CL:*178568
    BUG=chrome-os-partner:32684
    BRANCH=None
    TEST=Compiles successfully
    
    Original-Change-Id: I50d0475dbe1390b640a726c259364f36abcbebe0
    Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/221579
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
    
    (cherry picked from commit 14e348721399f13a52258faa16769b0ebb5b511f)
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    
    Change-Id: I2683cb29c7a93f3f4aba0d7b9a56a1ca209518a0
---
 src/mainboard/google/rush/Kconfig      |  5 +++-
 src/mainboard/google/rush/Makefile.inc |  5 ++++
 src/mainboard/google/rush/memlayout.ld |  4 +++
 src/mainboard/google/rush/verstage.c   | 51 ++++++++++++++++++++++++++++++++++
 4 files changed, 64 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig
index 94cbed1..95597b0 100644
--- a/src/mainboard/google/rush/Kconfig
+++ b/src/mainboard/google/rush/Kconfig
@@ -78,9 +78,12 @@ config BOOT_MEDIA_SPI_CHIP_SELECT
 	help
 	  Which chip select to use for boot media.
 
+# For rush, we are using vboot2. Thus, index for stages:
+# VBOOT_ROMSTAGE_INDEX -> Use default value of 0x2
+# VBOOT_RAMSTAGE_INDEX -> Use 0x3
 config VBOOT_RAMSTAGE_INDEX
 	hex
-	default 0x2
+	default 0x3
 
 config DRIVER_TPM_I2C_BUS
 	hex
diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc
index e41745f..a4d0135 100644
--- a/src/mainboard/google/rush/Makefile.inc
+++ b/src/mainboard/google/rush/Makefile.inc
@@ -31,6 +31,10 @@ bootblock-y += bootblock.c
 bootblock-y += pmic.c
 bootblock-y += reset.c
 
+verstage-y += verstage.c
+verstage-y += chromeos.c
+verstage-y += reset.c
+
 romstage-y += romstage.c
 romstage-y += sdram_configs.c
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
@@ -44,3 +48,4 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 bootblock-y += memlayout.ld
 romstage-y += memlayout.ld
 ramstage-y += memlayout.ld
+verstage-y += memlayout.ld
diff --git a/src/mainboard/google/rush/memlayout.ld b/src/mainboard/google/rush/memlayout.ld
index 85f4a97..5bd72e5 100644
--- a/src/mainboard/google/rush/memlayout.ld
+++ b/src/mainboard/google/rush/memlayout.ld
@@ -1 +1,5 @@
+#if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
+#include <soc/memlayout_vboot2.ld>
+#else
 #include <soc/memlayout_vboot.ld>
+#endif
diff --git a/src/mainboard/google/rush/verstage.c b/src/mainboard/google/rush/verstage.c
new file mode 100644
index 0000000..0150e46
--- /dev/null
+++ b/src/mainboard/google/rush/verstage.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <soc/addressmap.h>
+#include <soc/funitcfg.h>
+#include <soc/padconfig.h>
+#include <soc/verstage.h>
+#include <soc/nvidia/tegra/i2c.h>
+
+static const struct pad_config i2cpad[] = {
+	/* TPM I2C */
+	PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
+	PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
+};
+
+static const struct pad_config spipad[] = {
+	/* EC on SPI1: mosi, miso, clk, cs */
+	PAD_CFG_SFIO(ULPI_CLK, PINMUX_INPUT_ENABLE, SPI1),
+	PAD_CFG_SFIO(ULPI_DIR, PINMUX_INPUT_ENABLE, SPI1),
+	PAD_CFG_SFIO(ULPI_NXT, PINMUX_INPUT_ENABLE, SPI1),
+	PAD_CFG_SFIO(ULPI_STP, PINMUX_INPUT_ENABLE, SPI1),
+};
+
+static const struct funit_cfg funitcfgs[] = {
+	FUNIT_CFG(SBC1, CLK_M, 3000, spipad, ARRAY_SIZE(spipad)),
+	FUNIT_CFG(I2C3, PLLP, 400, i2cpad, ARRAY_SIZE(i2cpad)),
+};
+
+void verstage_mainboard_init(void)
+{
+	soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
+
+	/* TPM I2C bus */
+	i2c_init(2);
+}