[coreboot-gerrit] Patch merged into coreboot/master: 2d3d452 rk3288: configure l2ctlr in romstage

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 2d3d452d521db352b9f9a978314a997d3dee5bd6
Author: huang lin <hl at rock-chips.com>
Date:   Thu Oct 16 09:27:31 2014 -0700

    rk3288: configure l2ctlr in romstage
    
    Data RAM write latency: 2 cycles
    Data RAM read latency: 2 cycles
    Data RAM setup latency: 1 cycle
    Tag RAM write latency: 1 cycle
    Tag RAM read latency: 1 cycle
    Tag RAM setup latency: 1 cycle
    
    BUG=None
    TEST=Boot Veyron Pinky
    
    Change-Id: I1d710f65114be6a976aa3fe23b076e89c14ac8b8
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 421c2e5ba44f1693f8b3c869289fc93ab9ef5965
    Original-Change-Id: Ic9c909b7913d434bd40016c6a820ddff7e991634
    Original-Signed-off-by: huang lin <hl at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/223713
    Original-Reviewed-by: Doug Anderson <dianders at chromium.org>
    Original-Commit-Queue: Doug Anderson <dianders at chromium.org>
    Reviewed-on: http://review.coreboot.org/9347
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/9347 for details.

-gerrit