[coreboot-gerrit] Patch merged into coreboot/master: f8dcdea rk3288: Fix some PLL divisors and improve clock code

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit f8dcdea60973b729bf9eee0fb46dccf1b4b2aeb6
Author: Julius Werner <jwerner at chromium.org>
Date:   Mon Oct 6 15:02:12 2014 -0700

    rk3288: Fix some PLL divisors and improve clock code
    
    This patch does some general cleanup in the Rockchip clock code, and
    adds some more assertions regarding the PLL VCO and output frequency
    ranges. It changes all PLL divisors to use the lowest values that can
    still hit the target frequency, since higher NR values lead to higher
    jitter and higher NO values increase power draw.
    
    Also change DDR3 frequency code to hardcode the optimal divisors for
    certail frequencies. As a little hack we will interpret 666000000 to
    actually mean 666666666.6P (and analogous for 533MHz), since that's what
    you usually want for memory.
    
    BUG=chrome-os-partner:32139
    TEST=Boot on veyron_pinky rev2, check that dpll_is shown as 666666666 in
    /sys/kernel/debug/clk/clk_summary.
    
    Change-Id: I57d7ef34500984184e010c0cc7d73789338834d4
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7466ffc035b3f06ac280f412bc496059abf3239c
    Original-Change-Id: I4f3c39641955a95c6dfbe9334035eb670b138bf0
    Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/221801
    Reviewed-on: http://review.coreboot.org/9339
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/9339 for details.

-gerrit