[coreboot-gerrit] Patch merged into coreboot/master: fc934b2 mips: add c0 register access plumbing

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit fc934b2da280d64bf42d2947346558f7475d5481
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Wed Nov 5 17:51:19 2014 -0800

    mips: add c0 register access plumbing
    
    C0 is a coprocessor register set defined in certain MIPS
    architectures. This patch adds macros necessary to access the
    registers and a couple of helper macros to access two particular
    registers needed in the next patch.
    
    The definitions come straight from arch/mips/include/asm/mipsregs.h in
    the 3.14 kernel tree.
    
    BRANCH=none
    BUG=chrome-os-partner:31438
    TEST=the following patch demonstrates timer counter C0 register
         configuration and use.
    
    Change-Id: Ia5d52ffa75f2dd66d4cee3a4ed0af5122ccb2113
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: eb3d69eaf1561ca0b995720c24dafe2e6e22707d
    Original-Change-Id: Ia4b1da40ecc1a03cf1cba0c648d42cd189fbcf93
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/227887
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/9336
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/9336 for details.

-gerrit