[coreboot-gerrit] Patch set updated for coreboot: 245b157 arm: Dump additional fault registers in abort handlers
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Apr 7 13:55:12 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9345
-gerrit
commit 245b157f9f49682176d6cb9ebff27aac7c5b5e6f
Author: Julius Werner <jwerner at chromium.org>
Date: Thu Oct 16 10:23:36 2014 -0700
arm: Dump additional fault registers in abort handlers
Paging code is tricky and figuring out what is wrong with it can be a
pain. This patch tries to ease the burden by giving a little more
information for prefetch and data aborts, dumping the Instruction Fault
Address Register (IFAR), Instruction Fault Status Register (IFSR) and
Auxiliary Instruction Fault Status Register (AIFSR) or the respective
Data registers. These contain additional information about the cause of
the abort (internal/external, write or read, fault subtype, etc.) and
the faulting address.
BUG=None
TEST=I have read through enough imprecise asynchronous external abort
reports with this patch that I learned the bit pattern by heart.
Change-Id: If1850c4a6df29b1195714ed0bdf025e51220e8ab
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: bf3b4924121825a5ceef7e5c14b7b307d01f8e9c
Original-Change-Id: I56a0557d4257f40b5b30c559c84eaf9b9f729099
Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223784
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
payloads/libpayload/arch/arm/exception.c | 12 +++++++
payloads/libpayload/include/arm/arch/cache.h | 48 ++++++++++++++++++++++++++++
src/arch/arm/armv7/exception.c | 6 ++++
src/arch/arm/include/armv7/arch/cache.h | 48 ++++++++++++++++++++++++++++
4 files changed, 114 insertions(+)
diff --git a/payloads/libpayload/arch/arm/exception.c b/payloads/libpayload/arch/arm/exception.c
index d100937..6f17960 100644
--- a/payloads/libpayload/arch/arm/exception.c
+++ b/payloads/libpayload/arch/arm/exception.c
@@ -90,6 +90,18 @@ void exception_dispatch(u32 idx)
printf("%s Exception\n", names[idx]);
print_regs();
+ switch (idx) {
+ case EXC_PABORT:
+ printf("IFAR = %#.8x\n", read_ifar());
+ printf("IFSR = %#.8x\n", read_ifsr());
+ printf("AIFSR = %#.8x\n", read_aifsr());
+ break;
+ case EXC_DABORT:
+ printf("DFAR = %#.8x\n", read_dfar());
+ printf("DFSR = %#.8x\n", read_dfsr());
+ printf("ADFSR = %#.8x\n", read_adfsr());
+ break;
+ };
dump_stack(exception_state.regs[13], 512);
halt();
}
diff --git a/payloads/libpayload/include/arm/arch/cache.h b/payloads/libpayload/include/arm/arch/cache.h
index 67f6fd4..b258185 100644
--- a/payloads/libpayload/include/arm/arch/cache.h
+++ b/payloads/libpayload/include/arm/arch/cache.h
@@ -268,6 +268,54 @@ static inline void write_sctlr(uint32_t val)
isb();
}
+/* read data fault address register (DFAR) */
+static inline uint32_t read_dfar(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c6, c0, 0" : "=r" (val));
+ return val;
+}
+
+/* read data fault status register (DFSR) */
+static inline uint32_t read_dfsr(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c5, c0, 0" : "=r" (val));
+ return val;
+}
+
+/* read instruction fault address register (IFAR) */
+static inline uint32_t read_ifar(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c6, c0, 2" : "=r" (val));
+ return val;
+}
+
+/* read instruction fault status register (IFSR) */
+static inline uint32_t read_ifsr(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c5, c0, 1" : "=r" (val));
+ return val;
+}
+
+/* read auxiliary data fault status register (ADFSR) */
+static inline uint32_t read_adfsr(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c5, c1, 0" : "=r" (val));
+ return val;
+}
+
+/* read auxiliary instruction fault status register (AIFSR) */
+static inline uint32_t read_aifsr(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c5, c1, 1" : "=r" (val));
+ return val;
+}
+
/*
* Cache maintenance API
*/
diff --git a/src/arch/arm/armv7/exception.c b/src/arch/arm/armv7/exception.c
index eedd47d..4fac0bc 100644
--- a/src/arch/arm/armv7/exception.c
+++ b/src/arch/arm/armv7/exception.c
@@ -100,6 +100,9 @@ void exception_prefetch_abort(uint32_t *regs)
printk(BIOS_ERR, "exception _prefetch_abort\n");
regs[15] -= 4;
print_regs(regs);
+ printk(BIOS_ERR, "IFAR = %#.8x\n", read_ifar());
+ printk(BIOS_ERR, "IFSR = %#.8x\n", read_ifsr());
+ printk(BIOS_ERR, "AIFSR = %#.8x\n", read_aifsr());
dump_stack(regs[13], 512);
die("exception");
}
@@ -109,6 +112,9 @@ void exception_data_abort(uint32_t *regs)
printk(BIOS_ERR, "exception _data_abort\n");
regs[15] -= 8;
print_regs(regs);
+ printk(BIOS_ERR, "DFAR = %#.8x\n", read_dfar());
+ printk(BIOS_ERR, "DFSR = %#.8x\n", read_dfsr());
+ printk(BIOS_ERR, "ADFSR = %#.8x\n", read_adfsr());
dump_stack(regs[13], 512);
die("exception");
}
diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h
index f23dec1..12df5c3 100644
--- a/src/arch/arm/include/armv7/arch/cache.h
+++ b/src/arch/arm/include/armv7/arch/cache.h
@@ -295,6 +295,54 @@ static inline void write_sctlr(uint32_t val)
isb();
}
+/* read data fault address register (DFAR) */
+static inline uint32_t read_dfar(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c6, c0, 0" : "=r" (val));
+ return val;
+}
+
+/* read data fault status register (DFSR) */
+static inline uint32_t read_dfsr(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c5, c0, 0" : "=r" (val));
+ return val;
+}
+
+/* read instruction fault address register (IFAR) */
+static inline uint32_t read_ifar(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c6, c0, 2" : "=r" (val));
+ return val;
+}
+
+/* read instruction fault status register (IFSR) */
+static inline uint32_t read_ifsr(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c5, c0, 1" : "=r" (val));
+ return val;
+}
+
+/* read auxiliary data fault status register (ADFSR) */
+static inline uint32_t read_adfsr(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c5, c1, 0" : "=r" (val));
+ return val;
+}
+
+/* read auxiliary instruction fault status register (AIFSR) */
+static inline uint32_t read_aifsr(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c5, c1, 1" : "=r" (val));
+ return val;
+}
+
/*
* Cache maintenance API
*/
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