[coreboot-gerrit] Patch set updated for coreboot: c736e0e tegra132: remove framebuffer reservation

[Aaron Durbin (adurbin@google.com)]

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9256

-gerrit

commit c736e0e2a491a382fa631563aab71ee1146ab64b
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Oct 7 16:16:48 2014 -0500

    tegra132: remove framebuffer reservation
    
    There's no need to reserve the framebuffer within coreboot. If the
    payloads need a framebuffer they can allocate one themselves.
    
    BUG=chrome-os-partner:31355
    BRANCH=None
    TEST=Built and booted on ryu.
    
    Original-Change-Id: I8d8b159e7fdd877e392193c5474a7518e9b3ad21
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/221726
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
    
    (cherry picked from commit 1ff8da9fed414fceeda3f94b296312f4531b320f)
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    
    Change-Id: I4e7c0417824f2be9836b1bc2bb99322c78490ca2
---
 src/soc/nvidia/tegra132/addressmap.c             | 15 ---------------
 src/soc/nvidia/tegra132/cbmem.c                  | 22 +++++++++++-----------
 src/soc/nvidia/tegra132/include/soc/addressmap.h |  3 ---
 src/soc/nvidia/tegra132/include/soc/display.h    |  2 --
 src/soc/nvidia/tegra132/soc.c                    |  6 ------
 5 files changed, 11 insertions(+), 37 deletions(-)

diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c
index d7ade2f..3df15b7 100644
--- a/src/soc/nvidia/tegra132/addressmap.c
+++ b/src/soc/nvidia/tegra132/addressmap.c
@@ -22,7 +22,6 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <soc/addressmap.h>
-#include <soc/display.h>
 #include <soc/id.h>
 #include "mc.h"
 #include "sdram.h"
@@ -166,20 +165,6 @@ void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib)
 	memory_in_range(base_mib, end_mib, 0);
 }
 
-uintptr_t framebuffer_attributes(size_t *size_mib)
-{
-	uintptr_t begin;
-	uintptr_t end;
-
-	/* Place the framebuffer just below the 32-bit addressable limit. */
-	memory_in_range_below_4gb(&begin, &end);
-
-	*size_mib = FB_SIZE_MB;
-	end -= *size_mib;
-
-	return end;
-}
-
 void trustzone_region_init(void)
 {
 	struct tegra_mc_regs * const mc = (void *)(uintptr_t)TEGRA_MC_BASE;
diff --git a/src/soc/nvidia/tegra132/cbmem.c b/src/soc/nvidia/tegra132/cbmem.c
index da08520..e371298 100644
--- a/src/soc/nvidia/tegra132/cbmem.c
+++ b/src/soc/nvidia/tegra132/cbmem.c
@@ -23,18 +23,18 @@
 void *cbmem_top(void)
 {
 	static uintptr_t addr;
-	size_t fb_size;
 
-	/*
-	 * FIXME(adurbin): The TZ registers are not accessible to the AVP.
-	 * Therefore, if there is a TZ carveout then it needs to be handled
-	 * here while executing on the AVP in order to properly place the
-	 * CBMEM region.
-	 */
+	if (addr == 0) {
+		uintptr_t begin_mib;
+		uintptr_t end_mib;
 
-	/* CBMEM starts downwards from the framebuffer. */
-	if (addr == 0)
-		addr = framebuffer_attributes(&fb_size);
+		memory_in_range_below_4gb(&begin_mib, &end_mib);
+		/* Make sure we consume everything up to 4GiB. */
+		if (end_mib == 4096)
+			addr = ~(uint32_t)0;
+		else
+			addr = end_mib << 20;
+	}
 
-	return (void *)(addr << 20UL);
+	return (void *)addr;
 }
diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h
index ebe50f5..dc8ba61 100644
--- a/src/soc/nvidia/tegra132/include/soc/addressmap.h
+++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h
@@ -130,7 +130,4 @@ void mainboard_add_memory_ranges(struct memranges *map);
  */
 void trustzone_region_init(void);
 
-/* Return pointer and size in 1MiB units. */
-uintptr_t framebuffer_attributes(size_t *size_mib);
-
 #endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ */
diff --git a/src/soc/nvidia/tegra132/include/soc/display.h b/src/soc/nvidia/tegra132/include/soc/display.h
index 2c21292..a6cd1a4 100644
--- a/src/soc/nvidia/tegra132/include/soc/display.h
+++ b/src/soc/nvidia/tegra132/include/soc/display.h
@@ -197,6 +197,4 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
 		     u32 lane_count, u32 enhanced_framing, u32 panel_edp,
 		     u32 pclkfreq, u32 linkfreq);
 
-#define FB_SIZE_MB (32)
-
 #endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ */
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index 2c03db7..25a8e7e 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -47,12 +47,6 @@ static void soc_read_resources(device_t dev)
 		reserved_ram_resource(dev, index++, begin * KiB, size * KiB);
 	}
 
-	/*
-	 * TODO: Frame buffer needs to handled as a carveout from the below_4G
-	 * uintptr_t framebuffer_begin = framebuffer_attributes(&framebuffer_size);
-	 */
-
-
 	memory_in_range_below_4gb(&begin, &end);
 	size = end - begin;
 	ram_resource(dev, index++, begin * KiB, size * KiB);