[coreboot-gerrit] Patch set updated for coreboot: 52e7da7 build system: rename __BOOT_BLOCK__ and __VER_STAGE__
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Fri Apr 3 11:43:33 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9290
-gerrit
commit 52e7da7f3611e1b3ec114dd40dc1c40659acb709
Author: Patrick Georgi <pgeorgi at chromium.org>
Date: Thu Apr 2 19:44:19 2015 +0200
build system: rename __BOOT_BLOCK__ and __VER_STAGE__
Drop the inner underscore for consistency. Follows the
commit stated below.
Change-Id: I75cde6e2cd55d2c0fbb5a2d125c359d91e14cf6d
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Based-on-Change-Id: I6a1f25f7077328a8b5201a79b18fc4c2e22d0b06
Based-on-Signed-off-by: Julius Werner <jwerner at chromium.org>
Based-on-Reviewed-on: https://chromium-review.googlesource.com/219172
---
Makefile.inc | 2 +-
src/arch/x86/Makefile.inc | 4 ++--
src/console/init.c | 2 +-
src/cpu/allwinner/a10/clock.c | 4 ++--
src/include/rules.h | 2 +-
src/lib/cbfs_core.h | 2 +-
src/soc/intel/fsp_baytrail/baytrail/gpio.h | 8 ++++----
src/soc/samsung/exynos5250/gpio.c | 4 ++--
src/soc/samsung/exynos5420/gpio.c | 4 ++--
src/vendorcode/google/chromeos/Makefile.inc | 2 +-
10 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 155ba18..7abcbdf 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -132,7 +132,7 @@ ifeq ($(CONFIG_USE_BLOBS),y)
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty))
endif
-bootblock-generic-ccopts += -D__BOOT_BLOCK__ -D__PRE_RAM__
+bootblock-generic-ccopts += -D__BOOTBLOCK__ -D__PRE_RAM__
ramstage-c-deps:=$$(OPTION_TABLE_H)
romstage-c-deps:=$$(OPTION_TABLE_H)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9fa77d1..6f04f9c 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -98,9 +98,9 @@ endif
bootblock_inc += $(objgenerated)/bootblock.inc
bootblock_inc += $(src)/arch/x86/lib/walkcbfs.S
-bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOT_BLOCK__
+bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
ifeq ($(CONFIG_SSE),y)
-bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOT_BLOCK__
+bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
endif
$(objgenerated)/bootblock.ld: $(obj)/ldoptions $$(filter %.ld,$$(bootblock-srcs))
diff --git a/src/console/init.c b/src/console/init.c
index e638216..ee64d87 100644
--- a/src/console/init.c
+++ b/src/console/init.c
@@ -49,7 +49,7 @@ void console_init(void)
printk(BIOS_INFO, "\n\ncoreboot-%s%s %s %s starting...\n",
coreboot_version, coreboot_extra_version, coreboot_build,
-#if defined(__BOOT_BLOCK__)
+#if defined(__BOOTBLOCK__)
"bootblock"
#elif defined(__PRE_RAM__)
"romstage"
diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c
index f189aea..a8e2151 100644
--- a/src/cpu/allwinner/a10/clock.c
+++ b/src/cpu/allwinner/a10/clock.c
@@ -130,7 +130,7 @@ void a1x_gate_dram_clock_output(void)
* Linker doesn't garbage collect and the function below adds about half
* kilobyte to the bootblock, and log2_ceil is not available in the bootblock.
*/
-#ifndef __BOOT_BLOCK__
+#ifndef __BOOTBLOCK__
#define PLL1_CFG(N, K, M, P_EXP) \
((1 << 31 | 0 << 30 | 8 << 26 | 0 << 25 | 16 << 20 | 2 << 13) | \
@@ -270,4 +270,4 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz)
udelay(1);
}
-#endif /* __BOOT_BLOCK__ */
+#endif /* __BOOTBLOCK__ */
diff --git a/src/include/rules.h b/src/include/rules.h
index 5740b77..a99d3e2 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -23,7 +23,7 @@
* romstage, ramstage or SMM.
*/
-#if defined(__BOOT_BLOCK__)
+#if defined(__BOOTBLOCK__)
#define ENV_BOOTBLOCK 1
#define ENV_ROMSTAGE 0
#define ENV_RAMSTAGE 0
diff --git a/src/lib/cbfs_core.h b/src/lib/cbfs_core.h
index c1eecd2..221fe5d 100644
--- a/src/lib/cbfs_core.h
+++ b/src/lib/cbfs_core.h
@@ -13,7 +13,7 @@
# define CBFS_MINI_BUILD
#elif defined(__SMM__)
# define CBFS_MINI_BUILD
-#elif defined(__BOOT_BLOCK__)
+#elif defined(__BOOTBLOCK__)
/* No LZMA in boot block. */
#elif defined(__PRE_RAM__) && !CONFIG_COMPRESS_RAMSTAGE
/* No LZMA in romstage if ramstage is not compressed. */
diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
index e06c8d6..bdbb4a5 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
@@ -300,7 +300,7 @@
#define GPSSUS_GPIO_F1_RANGE_START 11
#define GPSSUS_GPIO_F1_RANGE_END 21
-#ifndef __BOOT_BLOCK__
+#ifndef __BOOTBLOCK__
struct soc_gpio_map {
u32 pad_conf0;
@@ -344,7 +344,7 @@ uint8_t read_ssus_gpio(uint8_t gpio_num);
void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
-#endif /* #ifndef __BOOT_BLOCK__ */
+#endif /* #ifndef __BOOTBLOCK__ */
/* Functions / defines for changing GPIOs in romstage */
/* SCORE Pad definitions. */
@@ -385,7 +385,7 @@ static inline void ssus_select_func(int pad, int func)
write32(pconf0_addr, reg);
}
-#ifndef __BOOT_BLOCK__
+#ifndef __BOOTBLOCK__
/* These functions require that the input pad be configured as an input GPIO */
static inline int score_get_gpio(int pad)
@@ -408,6 +408,6 @@ static inline void ssus_disable_internal_pull(int pad)
write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask);
}
-#endif /* #ifndef __BOOT_BLOCK__ */
+#endif /* #ifndef __BOOTBLOCK__ */
#endif /* _BAYTRAIL_GPIO_H_ */
diff --git a/src/soc/samsung/exynos5250/gpio.c b/src/soc/samsung/exynos5250/gpio.c
index 2a93328..3e50791 100644
--- a/src/soc/samsung/exynos5250/gpio.c
+++ b/src/soc/samsung/exynos5250/gpio.c
@@ -211,7 +211,7 @@ int gpio_set_value(unsigned gpio, int value)
*/
#define GPIO_DELAY_US 5
-#ifndef __BOOT_BLOCK__
+#ifndef __BOOTBLOCK__
/*
* FIXME(dhendrix): These functions use udelay, which has dependencies on
* pwm code and timer code. These aren't necessary for the bootblock and
@@ -252,7 +252,7 @@ int gpio_read_mvl3(unsigned gpio)
return value;
}
-#endif /* __BOOT_BLOCK__ */
+#endif /* __BOOTBLOCK__ */
/*
* Display Exynos GPIO information
diff --git a/src/soc/samsung/exynos5420/gpio.c b/src/soc/samsung/exynos5420/gpio.c
index 2b65eda..ac82bf7 100644
--- a/src/soc/samsung/exynos5420/gpio.c
+++ b/src/soc/samsung/exynos5420/gpio.c
@@ -211,7 +211,7 @@ int gpio_set_value(unsigned gpio, int value)
*/
#define GPIO_DELAY_US 15
-#ifndef __BOOT_BLOCK__
+#ifndef __BOOTBLOCK__
/*
* FIXME(dhendrix): These functions use udelay, which has dependencies on
* pwm code and timer code. These aren't necessary for the bootblock and
@@ -252,7 +252,7 @@ int gpio_read_mvl3(unsigned gpio)
return value;
}
-#endif /* __BOOT_BLOCK__ */
+#endif /* __BOOTBLOCK__ */
/*
* Display Exynos GPIO information
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index 91287b5..c445135 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -96,7 +96,7 @@ VB_SOURCE := vboot_reference
CPPFLAGS_common += -I$(VB_SOURCE)/firmware/2lib/include
CPPFLAGS_common += -I$(VB_SOURCE)/firmware/include
-verstage-generic-ccopts += -D__PRE_RAM__ -D__VER_STAGE__
+verstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__
ifeq ($(CONFIG_RETURN_FROM_VERSTAGE),y)
bootblock-y += verstub.c chromeos.c
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