[coreboot-gerrit] New patch to review for coreboot: 36777b6 Broadwell: Pass TSC value to romstage_main

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9280

-gerrit

commit 36777b6d14f89856e3930746a5e20a5adb368b3e
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Thu Nov 20 16:56:44 2014 -0800

    Broadwell: Pass TSC value to romstage_main
    
    The romstage_main routine takes three parameters: bist, tsc_low and
    tsc_hi.  However in cache_as_ram.inc only the bist value is being
    passed.  This patch adds the two halves of the TSC value.
    
    BRANCH=none
    BUG=None
    TEST=Build and run on Samus
    
    Change-Id: I3d216edd0be65f29b51a66ed67b2d17910a594d4
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: de565f28dce8a549d74defbcf5eaf8116bb1b831
    Original-Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
    Original-Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e
    Original-Reviewed-on: https://chromium-review.googlesource.com/231173
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/broadwell/romstage/cache_as_ram.inc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index 4e6cf09..a10ca4c 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -180,7 +180,13 @@ clear_mtrrs:
 
 	/* Restore the BIST result. */
 	movl	%ebp, %eax
+
+	/* Build the call frame. */
 	movl	%esp, %ebp
+	movd	%mm1, %ebx
+	pushl	%ebx
+	movd	%mm0, %ebx
+	pushl	%ebx
 	pushl	%eax
 
 before_romstage: