[coreboot-gerrit] Patch set updated for coreboot: 288b93d pistachio: set correct CBMEM top address

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9191

-gerrit

commit 288b93d3602a50fce81e14343d7bed83436e44cb
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Sat Nov 29 15:31:40 2014 -0800

    pistachio: set correct CBMEM top address
    
    This is required for proper dynamic CBMEM operation.
    
    BRANCH=none
    BUG=chrome-os-partner:31438
    TEST=urara ramstage does not crash anymore in CBMEM initialization
    
    Change-Id: Id8e001be20fc245c91b2639f89775e594b0de966
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: b7c6e4090d76a172c269bff002428015cc8aac8a
    Original-Change-Id: I5d44907443724891c8cff805208a7a3bb8e36752
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/232292
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/imgtec/pistachio/cbmem.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c
index 5fb6c0e..1aed030 100644
--- a/src/soc/imgtec/pistachio/cbmem.c
+++ b/src/soc/imgtec/pistachio/cbmem.c
@@ -21,9 +21,9 @@
 
 #include <cbmem.h>
 #include <stdlib.h>
+#include <symbols.h>
 
 void *cbmem_top(void)
 {
-	uintptr_t top = MIN(CONFIG_DRAM_SIZE_MB, 256) << 20;
-	return (void *)(top + CONFIG_SYS_SDRAM_BASE);
+	return _dram + (CONFIG_DRAM_SIZE_MB << 20);
 }