[coreboot-gerrit] Patch merged into coreboot/master: b71d9b8 Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit b71d9b8a0f02d5f458620cb21cdfe7799b1faf84
Author: Kenji Chen <kenji.chen at intel.com>
Date:   Fri Oct 10 03:08:15 2014 +0800

    Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings.
    
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    BUG=chrome-os-partner:31424
    TEST=Build an image and confirm the settings are correctly applied
         to registers for PCIe L1 Sub-State feature enabling.
    
    Original-Commit-Id: b94c8c715febe3a04bfdf52f7b69d73ece0f6faf
    Original-Signed-off-by: Kenji Chen <kenji.chen at intel.com>
    Original-Change-Id: I07ce6eea648b1b37d606f5529edad184e3de70ac
    Original-Reviewed-on: https://chromium-review.googlesource.com/222599
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    
    Change-Id: I07336599797c09bf23e5b15059d6ad812fdc7c61
    Reviewed-on: http://review.coreboot.org/9223
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>


See http://review.coreboot.org/9223 for details.

-gerrit