[coreboot-gerrit] New patch to review for coreboot: 7878884 rockchip: support i2c clock setting
Aaron Durbin (adurbin@google.com)
gerrit at coreboot.org
Thu Apr 2 20:47:45 CEST 2015
Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9241
-gerrit
commit 78788849fe5f7fddbde001339ffcf8b34553be14
Author: huang lin <hl at rock-chips.com>
Date: Sat Sep 27 12:02:27 2014 +0800
rockchip: support i2c clock setting
BUG=None
TEST=Boot Veyron Pinky and measure i2c clock frequency
Original-Change-Id: I04d9fa75a05280885f083a828f78cf55811ca97d
Original-Signed-off-by: huang lin <hl at rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219660
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
Original-Commit-Queue: Julius Werner <jwerner at chromium.org>
Change-Id: Ie7ac3f2d0d76a4d3347bd469bf7af3295cc454fd
(cherry picked from commit 4b9b3c2f8b7c6cd189cb8f239508431ee08ebc52)
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/veyron_pinky/mainboard.c | 3 +++
src/soc/rockchip/rk3288/Makefile.inc | 1 +
src/soc/rockchip/rk3288/bootblock.c | 5 ++++
src/soc/rockchip/rk3288/clock.c | 2 +-
src/soc/rockchip/rk3288/clock.h | 1 -
src/soc/rockchip/rk3288/i2c.c | 39 +++++++++++++++++++++++++++
src/soc/rockchip/rk3288/i2c.h | 26 ++++++++++++++++++
7 files changed, 75 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c
index 22c9b0e..232010d 100644
--- a/src/mainboard/google/veyron_pinky/mainboard.c
+++ b/src/mainboard/google/veyron_pinky/mainboard.c
@@ -31,6 +31,7 @@
#include <soc/rockchip/rk3288/clock.h>
#include <soc/rockchip/rk3288/rk808.h>
#include <soc/rockchip/rk3288/spi.h>
+#include <soc/rockchip/rk3288/i2c.h>
#include "board.h"
@@ -81,6 +82,7 @@ static void configure_emmc(void)
static void configure_codec(void)
{
writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */
+ i2c_init(2, 400000); /* CODEC I2C */
writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
@@ -124,6 +126,7 @@ static void mainboard_init(device_t dev)
{
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); /* PMIC I2C */
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); /* PMIC I2C */
+ i2c_init(0, 400000); /* PMIC I2C */
gpio_output(GPIO_RESET, 0);
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index 37abe57..95d72c9 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -30,6 +30,7 @@ bootblock-y += clock.c
bootblock-y += spi.c
bootblock-y += media.c
bootblock-y += gpio.c
+bootblock-y += i2c.c
verstage-y += monotonic_timer.c
verstage-y += spi.c
diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c
index 635eee4..d7bc67a 100644
--- a/src/soc/rockchip/rk3288/bootblock.c
+++ b/src/soc/rockchip/rk3288/bootblock.c
@@ -26,6 +26,7 @@
#include "grf.h"
#include "spi.h"
#include <vendorcode/google/chromeos/chromeos.h>
+#include <soc/rockchip/rk3288/i2c.h>
static void bootblock_cpu_init(void)
{
@@ -34,11 +35,15 @@ static void bootblock_cpu_init(void)
writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
/*i2c1 for tpm*/
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+
/* spi0 for chrome ec */
writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
rk3288_init_timer();
console_init();
rkclk_init();
+
+ /*i2c1 for tpm 400khz*/
+ i2c_init(1, 400000);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
setup_chromeos_gpios();
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index d106245..8202ef2 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -157,8 +157,8 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 4);
* aclk_periph =
* periph_clk_src / (peri_aclk_div_con + 1)
*/
+#define PERI_ACLK_DIV_SHIFT (0x0)
#define PERI_ACLK_DIV_MSK (0x1F)
-#define PERI_ACLK_DIV_SHIFT (0)
/*******************CLKSEL37 BITS***************************/
#define L2_DIV_MSK (0x7)
diff --git a/src/soc/rockchip/rk3288/clock.h b/src/soc/rockchip/rk3288/clock.h
index c28d181..b206baa 100644
--- a/src/soc/rockchip/rk3288/clock.h
+++ b/src/soc/rockchip/rk3288/clock.h
@@ -40,5 +40,4 @@ void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n);
void rkclk_configure_ddr(unsigned int hz);
void rkclk_configure_i2s(unsigned int hz);
-
#endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */
diff --git a/src/soc/rockchip/rk3288/i2c.c b/src/soc/rockchip/rk3288/i2c.c
index 9348b6c..142ec4a 100644
--- a/src/soc/rockchip/rk3288/i2c.c
+++ b/src/soc/rockchip/rk3288/i2c.c
@@ -30,6 +30,9 @@
#include "addressmap.h"
#include "grf.h"
#include "soc.h"
+#include "i2c.h"
+#include "clock.h"
+
#define RETRY_COUNT 3
/* 100000us = 100ms */
#define I2C_TIMEOUT_US 100000
@@ -275,3 +278,39 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count)
}
return res;
}
+
+void i2c_init(unsigned int bus, unsigned int hz)
+{
+ unsigned int clk_div;
+ unsigned int divl;
+ unsigned int divh;
+ unsigned int i2c_src_clk;
+ struct rk3288_i2c_regs *regs = i2c_bus[bus];
+
+ /*i2c0,i2c2 src clk from pd_bus_pclk
+ other i2c src clk from peri_pclk
+ */
+ switch (bus) {
+ case 0:
+ case 2:
+ i2c_src_clk = PD_BUS_PCLK_HZ;
+ break;
+ case 1:
+ case 3:
+ case 4:
+ case 5:
+ i2c_src_clk = PERI_PCLK_HZ;
+ break;
+ default:
+ break;
+ }
+
+ /*SCL Divisor = 8*(CLKDIVL + 1 + CLKDIVH + 1)
+ SCL = PCLK/ SCLK Divisor
+ */
+ clk_div = div_round_up(i2c_src_clk, hz * 8) - 2;
+ divh = clk_div / 2;
+ divl = ALIGN_UP(clk_div, 2) / 2;
+ assert((divh < 65536) && (divl < 65536));
+ writel((divh << 16) | (divl << 0), ®s->i2c_clkdiv);
+}
diff --git a/src/soc/rockchip/rk3288/i2c.h b/src/soc/rockchip/rk3288/i2c.h
new file mode 100644
index 0000000..84d9b75
--- /dev/null
+++ b/src/soc/rockchip/rk3288/i2c.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3288_I2C_H__
+#define __SOC_ROCKCHIP_RK3288_I2C_H__
+
+void i2c_init(unsigned int bus, unsigned int hz);
+
+#endif
+
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