[coreboot-gerrit] New patch to review for coreboot: 587b27c veyron: select rw romstage using vboot2
Aaron Durbin (adurbin@google.com)
gerrit at coreboot.org
Thu Apr 2 19:33:46 CEST 2015
Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9234
-gerrit
commit 587b27c59e7ef1d56c56055bc6ffc5cd05e75333
Author: Daisuke Nojiri <dnojiri at chromium.org>
Date: Wed Sep 24 09:39:16 2014 -0700
veyron: select rw romstage using vboot2
this change makes veyron pinky to select a rw romstage using vboot2.
BUG=None
TEST=Booted Veyron Pinky. Verified firmware selection in the log.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri at chromium.org>
CQ-DEPEND=CL:219100
Original-Change-Id: Ia1cfdacde9f8b17b00e7772a02e0d266afedb82f
Original-Reviewed-on: https://chromium-review.googlesource.com/219103
Original-Reviewed-by: Daisuke Nojiri <dnojiri at chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri at chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri at chromium.org>
(cherry picked from commit 69c1e4b9ee200645d38d28165389aa85ef9b36cd)
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Change-Id: I7b4a2db8bcb95038dfb55bb7ceee66ac4a6c9475
---
src/mainboard/google/veyron_pinky/Kconfig | 5 +++++
src/mainboard/google/veyron_pinky/Makefile.inc | 2 ++
src/mainboard/google/veyron_pinky/mainboard.c | 5 -----
src/mainboard/google/veyron_pinky/romstage.c | 10 ++++++++--
src/soc/rockchip/rk3288/Kconfig | 21 +++++++++++++++++----
src/soc/rockchip/rk3288/Makefile.inc | 10 ++++++++++
src/soc/rockchip/rk3288/bootblock.c | 7 +++++++
src/soc/rockchip/rk3288/media.c | 2 +-
8 files changed, 50 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig
index e2c9d1a..07b31ff 100644
--- a/src/mainboard/google/veyron_pinky/Kconfig
+++ b/src/mainboard/google/veyron_pinky/Kconfig
@@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_4096
select MAINBOARD_HAS_BOOTBLOCK_INIT
select HAVE_HARD_RESET
+ select RETURN_FROM_VERSTAGE
config MAINBOARD_DIR
string
@@ -48,6 +49,10 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
default 0
+config VBOOT_RAMSTAGE_INDEX
+ hex
+ default 0x3
+
config BOOT_MEDIA_SPI_BUS
int
default 2
diff --git a/src/mainboard/google/veyron_pinky/Makefile.inc b/src/mainboard/google/veyron_pinky/Makefile.inc
index 2d3f62f..63fefe4 100644
--- a/src/mainboard/google/veyron_pinky/Makefile.inc
+++ b/src/mainboard/google/veyron_pinky/Makefile.inc
@@ -17,8 +17,10 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
bootblock-y += bootblock.c
+bootblock-y += chromeos.c
bootblock-y += reset.c
+verstage-y += chromeos.c
verstage-y += reset.c
romstage-y += romstage.c
diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c
index 4d647d3..0bbd496 100644
--- a/src/mainboard/google/veyron_pinky/mainboard.c
+++ b/src/mainboard/google/veyron_pinky/mainboard.c
@@ -57,13 +57,9 @@ static void setup_iomux(void)
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- /*i2c1 for tpm*/
- writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
-
/*i2c2 for codec*/
writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2);
- writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
@@ -127,7 +123,6 @@ static void mainboard_init(device_t dev)
configure_sdmmc();
configure_emmc();
configure_i2s();
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
}
static void mainboard_enable(device_t dev)
diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c
index e1062ca..31317a0 100644
--- a/src/mainboard/google/veyron_pinky/romstage.c
+++ b/src/mainboard/google/veyron_pinky/romstage.c
@@ -18,6 +18,7 @@
*/
#include <types.h>
+#include <arch/stages.h>
#include <armv7.h>
#include <cbfs.h>
#include <console/console.h>
@@ -68,8 +69,6 @@ void main(void)
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
dcache_mmu_enable();
- setup_chromeos_gpios();
-
cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS
@@ -79,5 +78,12 @@ void main(void)
timestamp_add(TS_AFTER_INITRAM, after_dram_time);
timestamp_add_now(TS_END_ROMSTAGE);
#endif
+
+#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE)
+ void *entry = vboot_load_ramstage();
+ if (entry != NULL)
+ stage_exit(entry);
+#endif
+
run_ramstage();
}
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig
index 359ce2f..aa4ee34 100644
--- a/src/soc/rockchip/rk3288/Kconfig
+++ b/src/soc/rockchip/rk3288/Kconfig
@@ -29,7 +29,6 @@ config SOC_ROCKCHIP_RK3288
select HAVE_UART_MEMORY_MAPPED
select HAVE_UART_SPECIAL
select BOOTBLOCK_CONSOLE
- select DYNAMIC_CBMEM
if SOC_ROCKCHIP_RK3288
@@ -49,9 +48,10 @@ config BOOTBLOCK_CPU_INIT
#
# 0xFF70_0000 TTB (16KB).
# 0xFF70_4004 Bootblock (max 16KB-4B).
-# 0xFF70_8000 ROM stage (max 40KB).
+# 0xFF70_8000 verstage then romstage (max 40KB).
# 0xFF71_2000 STACK (4KB).
-# 0xFF71_3000 CBFS mapping cache (20K)
+# 0xFF71_3000 CBFS mapping cache (4K)
+# 0xFF71_4000 vboot work buffer (16K)
# 0xFF71_7FFF End of iRAM.
config SYS_SRAM_BASE
@@ -74,6 +74,11 @@ config BOOTBLOCK_BASE
hex
default 0xff704004
+# with vboot2, romstage is loaded over the verstage space
+config VERSTAGE_BASE
+ hex
+ default 0xff708000
+
config ROMSTAGE_BASE
hex "ROM STAGE BASE"
default 0xff708000
@@ -100,7 +105,15 @@ config CBFS_SRAM_CACHE_ADDRESS
config CBFS_SRAM_CACHE_SIZE
hex "size of CBFS cache data"
- default 0x00005000
+ default 0x00001000
+
+config VBOOT_WORK_BUFFER_ADDRESS
+ hex "memory address of vboot work buffer"
+ default 0xff714000
+
+config VBOOT_WORK_BUFFER_SIZE
+ hex "size of vboot work buffer"
+ default 0x00004000
config CBFS_DRAM_CACHE_ADDRESS
hex "dram memory address to put CBFS cache data"
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index f9aa377..095c555 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -29,6 +29,16 @@ bootblock-y += monotonic_timer.c
bootblock-y += clock.c
bootblock-y += spi.c
bootblock-y += media.c
+bootblock-y += gpio.c
+
+verstage-y += monotonic_timer.c
+verstage-y += spi.c
+verstage-y += timer.c
+verstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c
+verstage-y += gpio.c
+verstage-y += clock.c
+verstage-y += i2c.c
+verstage-y += media.c
romstage-y += cbmem.c
romstage-y += timer.c
diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c
index 76a91d2..635eee4 100644
--- a/src/soc/rockchip/rk3288/bootblock.c
+++ b/src/soc/rockchip/rk3288/bootblock.c
@@ -25,14 +25,21 @@
#include "clock.h"
#include "grf.h"
#include "spi.h"
+#include <vendorcode/google/chromeos/chromeos.h>
static void bootblock_cpu_init(void)
{
writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
+ /*i2c1 for tpm*/
+ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+ /* spi0 for chrome ec */
+ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
rk3288_init_timer();
console_init();
rkclk_init();
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS);
+ rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
+ setup_chromeos_gpios();
}
diff --git a/src/soc/rockchip/rk3288/media.c b/src/soc/rockchip/rk3288/media.c
index 1389eb2..c6ceeb9 100644
--- a/src/soc/rockchip/rk3288/media.c
+++ b/src/soc/rockchip/rk3288/media.c
@@ -24,7 +24,7 @@
int init_default_cbfs_media(struct cbfs_media *media)
{
-#if defined(__BOOT_BLOCK__)
+#if defined(__BOOT_BLOCK__) || defined(__VER_STAGE__)
return initialize_rockchip_spi_cbfs_media(media,
(void *)CONFIG_CBFS_SRAM_CACHE_ADDRESS,
CONFIG_CBFS_SRAM_CACHE_SIZE);
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