[coreboot-gerrit] Patch merged into coreboot/master: 074a028 Samus: Synchronization with FRC to enable PCIe Relaxed Order.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 074a028ef715763ecda99386d472c751092150a1
Author: Kenji Chen <kenji.chen at intel.com>
Date:   Sat Sep 20 01:39:20 2014 +0800

    Samus: Synchronization with FRC to enable PCIe Relaxed Order.
    
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 8455d95442ee9a39ecb182abf319469dde06d324
    Original-BUG=None
    Original-TEST=Modify settings, build and update the image to Samus and
    Original-check the settings are applied to Registers.
    Original-Signed-off-by: Kenji Chen <kenji.chen at intel.com>
    Original-Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f
    Original-Reviewed-on: https://chromium-review.googlesource.com/219073
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    
    Change-Id: Ide6e747f1eccb74be2e21e76f592a919399bee31
    Reviewed-on: http://review.coreboot.org/9206
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/9206 for details.

-gerrit