[coreboot-gerrit] Patch set updated for coreboot: e7a7e8f samus: Ensure PD controller is in RO mode for recovery

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9205

-gerrit

commit e7a7e8fc1206a8f5e5a9e3809c4a57356d0f751a
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 18 12:56:04 2014 -0700

    samus: Ensure PD controller is in RO mode for recovery
    
    In order to not break FAFT, and to have a quicker recovery
    mode boot, reboot the PD controller into RO image in romstage.
    
    This is done before the EC since rebooting the EC into RO will
    also reboot the host.
    
    BUG=chrome-os-partner:30079
    BRANCH=none
    TEST=boot samus EVT into recovery with 'dut-control power_state:rec'
    and ensure that the PD controller is rebooted to RO in romstage.
    
    Change-Id: Ieb51717c17fdcbda7aa63b6a9404959e8736c08f
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 19237f6a338fa1c593867d8dfda1edcd376878af
    Original-Change-Id: I633f51afc382a7faab825c15618c0bc7566c4395
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/218904
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/samus/romstage.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c
index 44d712e..ca43b81 100644
--- a/src/mainboard/google/samus/romstage.c
+++ b/src/mainboard/google/samus/romstage.c
@@ -43,7 +43,8 @@ void mainboard_romstage_entry(struct romstage_params *rp)
 	printk(BIOS_INFO, "MLB: board version %d\n",
 	       google_chromeec_get_board_version());
 
-	/* Ensure the EC is in the right mode for recovery */
+	/* Ensure the EC and PD are in the right mode for recovery */
+	google_chromeec_early_pd_init();
 	google_chromeec_early_init();
 
 	/* Initialize GPIOs */