[coreboot-gerrit] Patch set updated for coreboot: 52046d3 Broadwell: Synchronization with FRC for RO, Link Arbiter, and OBFF.

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9210

-gerrit

commit 52046d392e79ec965961842864b5164ad22a953a
Author: Kenji Chen <kenji.chen at intel.com>
Date:   Fri Sep 26 02:48:16 2014 +0800

    Broadwell: Synchronization with FRC for RO, Link Arbiter, and OBFF.
    
    OBFF: Disable it by clear bit fields in that W/O register.
    RO: Enable Relaxed Ordering from each enabled Root Port.
    Linker Arbiter: Set it to recommeded setting.
    
    BUG=None
    TEST=Build a image and check the setting are applied correctly on
    Samub.
    Signed-off-by: Kenji Chen <kenji.chen at intel.com>
    
    Change-Id: I7a72217729d6f6ff5320738245c380c887c5912f
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 465b0a37c381930a4f0d74cd4fd69503a082911b
    Original-Change-Id: I284e9eba1c2fceb690d3ef48b45a6f36d07ff84c
    Original-Reviewed-on: https://chromium-review.googlesource.com/219993
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Commit-Queue: Kenji Chen <kenji.chen at intel.com>
    Original-Tested-by: Kenji Chen <kenji.chen at intel.com>
---
 src/soc/intel/broadwell/pcie.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 22eaab9..ccf089f 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -523,8 +523,8 @@ static void pch_pcie_early(struct device *dev)
 		pcie_update_cfg(dev, 0x338, ~(1 << 26), 0);
 	}
 
-	/* Enable LTR in Root Port. */
-	pcie_update_cfg(dev, 0x64, ~(1 << 11), (1 << 11));
+	/* Enable LTR in Root Port. Disbale OBFF. */
+	pcie_update_cfg(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11));
 	pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10));
 
 	pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
@@ -550,6 +550,11 @@ static void pch_pcie_early(struct device *dev)
 	/* Set Extended Capability to offset 200h and Advanced Error Report. */
 	pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001);
 
+	pcie_update_cfg(dev, 0x320, ~(3 << 20) & ~(7 << 6),
+		(1 << 20) | (3 << 6));
+	/* Enable Relaxed Order from Root Port. */
+	pcie_update_cfg(dev, 0x320, ~(3 << 23), (3 << 23));
+
 	if (rp == 1 || rp == 5 || rp == 6)
 		pcie_update_cfg8(dev, 0xf7, ~0xc, 0);