[coreboot-gerrit] Patch merged into coreboot/master: e237f5a Baytrail: Change PCIe root disable algorithm

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit e237f5ac95edb227106a888738771755194c82cd
Author: Kenji Chen <kenji.chen at intel.com>
Date:   Fri Sep 12 02:10:53 2014 +0800

    Baytrail: Change PCIe root disable algorithm
    
    Disable Root Port0 only when there is no PCIe device
    present on any root port.
    
    BUG=None
    TEST=Boot Rambi with PCIe installed/non-installed on RP0 to
    confirm the RP0 is correctly enabled/disabled. However, I still
    need someone to help check if RP0(no device) is still enabled
    if there is device on other RPs since since I have no devices
    having slots from RP1/2/3.
    
    Change-Id: Iae552975250ed6f309c423b847621b8994172891
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: c5cef0b7c2c146f0d46ed49b75fd2ec8369210ce
    Original-Change-Id: I7147569e78b2d1ecea070bc933773cdcae59f9e7
    Original-Signed-off-by: Kenji Chen <kenji.chen at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/217791
    Original-Tested-by: Ted Kuo <tedkuo at ami.com.tw>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/9219
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/9219 for details.

-gerrit