[coreboot-gerrit] New patch to review for coreboot: ad1faec Baytrail: add _PRT to each PCIe root port device

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9201

-gerrit

commit ad1faecaf89cd369362133610d465198a4436cf6
Author: Ted Kuo <tedkuo at ami.com.tw>
Date:   Tue Sep 16 15:31:21 2014 +0800

    Baytrail: add _PRT to each PCIe root port device
    
    Report PCI routing table of all PCIe root ports for legacy interrupt.
    Some PCIe devices using legacy interrupt can't work if PCI routing table
    isn't defined. It's necessary and defined in BWG Chapter 28.1.3.
    
    BUG=chrome-os-partner:31943
    TEST=compiled and tested
    BRANCH=NONE
    Signed-off-by: Ted Kuo <tedkuo at ami.com.tw>
    
    Change-Id: I2c684edfd1fc624bed471783584250cd9f5e66f5
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: b9040d564a32607327057a84b9aab14e66cd5b45
    Original-Change-Id: Ia15ced6c5fdcc6712e5f2831e42c6dee320f166b
    Original-Reviewed-on: https://chromium-review.googlesource.com/218422
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Ted Kuo <tedkuo at ami.com.tw>
    Original-Commit-Queue: Ted Kuo <tedkuo at ami.com.tw>
    Original-Tested-by: Ted Kuo <tedkuo at ami.com.tw>
---
 src/soc/intel/baytrail/acpi/pcie.asl         | 109 +++++++++++++++++++++++++++
 src/soc/intel/baytrail/acpi/southcluster.asl |   3 +
 2 files changed, 112 insertions(+)

diff --git a/src/soc/intel/baytrail/acpi/pcie.asl b/src/soc/intel/baytrail/acpi/pcie.asl
new file mode 100644
index 0000000..5ad4e78
--- /dev/null
+++ b/src/soc/intel/baytrail/acpi/pcie.asl
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Intel SOC PCIe support */
+
+Device (RP01)
+{
+	Name (_ADR, 0x001c0000)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
+			})
+		}
+	}
+}
+
+Device (RP02)
+{
+	Name (_ADR, 0x001c0001)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
+			})
+		}
+	}
+}
+
+Device (RP03)
+{
+	Name (_ADR, 0x001c0002)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
+			})
+		}
+	}
+}
+
+Device (RP04)
+{
+	Name (_ADR, 0x001c0003)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
+			})
+		}
+	}
+}
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 5382182..354515b 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -254,6 +254,9 @@ Device (IOSF)
 // IRQ routing for each PCI device
 #include "irqroute.asl"
 
+// PCI Express Ports 0:1c.x
+#include "pcie.asl"
+
 Scope (\_SB)
 {
 	// GPIO Devices