[coreboot-gerrit] Patch set updated for coreboot: 54543f5 mainboard/supermicro/h8qme_fam10: Fix indentations and spelling
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Wed Apr 1 21:22:25 CEST 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9177
-gerrit
commit 54543f5db2c2f118714e4b0bbb9ffdd35d23a8fc
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Tue Mar 31 11:54:03 2015 -0500
mainboard/supermicro/h8qme_fam10: Fix indentations and spelling
Change-Id: I49c5d39a674351f7375fb762fc9ef4a3700d7c87
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/mainboard/supermicro/h8qme_fam10/romstage.c | 181 ++++++++++++------------
1 file changed, 91 insertions(+), 90 deletions(-)
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 7a75159..8583f2a 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -50,10 +50,11 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
#define SMBUS_SWITCH1 0x70
#define SMBUS_SWITCH2 0x72
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
}
@@ -77,36 +78,36 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
- uint32_t dword;
- uint8_t byte;
- enable_smbus();
+ uint32_t dword;
+ uint8_t byte;
+ enable_smbus();
// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
+ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+ byte |= 0x20;
+ pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+ dword |= (1<<0);
+ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1<<16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
+ dword |= (1<<16);
+ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
}
static const u8 spd_addr[] = {
- //first node
+ /* first node */
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
- //second node
+ /* second node */
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
- //third node
+ /* third node */
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
- //forth node
+ /* fourth node */
RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
#endif
};
@@ -183,12 +184,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sio_setup();
}
- post_code(0x30);
+ post_code(0x30);
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- post_code(0x32);
+ post_code(0x32);
w83627hf_set_clksel_48(DUMMY_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -200,113 +201,113 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
- /* Setup sysinfo defaults */
- set_sysinfo_in_ram(0);
+ /* Setup sysinfo defaults */
+ set_sysinfo_in_ram(0);
- update_microcode(val);
+ update_microcode(val);
- post_code(0x33);
+ post_code(0x33);
- cpuSetAMDMSR();
- post_code(0x34);
+ cpuSetAMDMSR();
+ post_code(0x34);
- amd_ht_init(sysinfo);
- post_code(0x35);
+ amd_ht_init(sysinfo);
+ post_code(0x35);
- /* Setup nodes PCI space and start core 0 AP init. */
- finalize_node_setup(sysinfo);
+ /* Setup nodes PCI space and start core 0 AP init. */
+ finalize_node_setup(sysinfo);
- /* Setup any mainboard PCI settings etc. */
- setup_mb_resource_map();
- post_code(0x36);
+ /* Setup any mainboard PCI settings etc. */
+ setup_mb_resource_map();
+ post_code(0x36);
- /* wait for all the APs core0 started by finalize_node_setup. */
- /* FIXME: A bunch of cores are going to start output to serial at once.
- * It would be nice to fixup prink spinlocks for ROM XIP mode.
- * I think it could be done by putting the spinlock flag in the cache
- * of the BSP located right after sysinfo.
- */
+ /* wait for all the APs core0 started by finalize_node_setup. */
+ /* FIXME: A bunch of cores are going to start output to serial at once.
+ * It would be nice to fixup prink spinlocks for ROM XIP mode.
+ * I think it could be done by putting the spinlock flag in the cache
+ * of the BSP located right after sysinfo.
+ */
- wait_all_core0_started();
+ wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
- /* Core0 on each node is configured. Now setup any additional cores. */
- printk(BIOS_DEBUG, "start_other_cores()\n");
- start_other_cores();
- post_code(0x37);
- wait_all_other_cores_started(bsp_apicid);
+ /* Core0 on each node is configured. Now setup any additional cores. */
+ printk(BIOS_DEBUG, "start_other_cores()\n");
+ start_other_cores();
+ post_code(0x37);
+ wait_all_other_cores_started(bsp_apicid);
#endif
- post_code(0x38);
+ post_code(0x38);
#if CONFIG_SET_FIDVID
- msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
+ msr = rdmsr(0xc0010071);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
- /* FIXME: The sb fid change may survive the warm reset and only
- * need to be done once.*/
+ /* FIXME: The sb fid change may survive the warm reset and only
+ * need to be done once.*/
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- post_code(0x39);
+ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+ post_code(0x39);
- if (!warm_reset_detect(0)) { // BSP is node 0
- init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
- } else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
- }
+ if (!warm_reset_detect(0)) { // BSP is node 0
+ init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
+ } else {
+ init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ }
- post_code(0x3A);
+ post_code(0x3A);
- /* show final fid and vid */
- msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
+ /* show final fid and vid */
+ msr=rdmsr(0xc0010071);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
init_timer(); // Need to use TMICT to synchronize FID/VID
- wants_reset = mcp55_early_setup_x();
+ wants_reset = mcp55_early_setup_x();
- /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
- if (!warm_reset_detect(0)) {
- printk(BIOS_INFO, "...WARM RESET...\n\n\n");
- soft_reset();
- die("After soft_reset_x - shouldn't see this message!!!\n");
- }
+ /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+ if (!warm_reset_detect(0)) {
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
+ soft_reset();
+ die("After soft_reset_x - shouldn't see this message!!!\n");
+ }
- if (wants_reset)
- printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
+ if (wants_reset)
+ printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
- post_code(0x3B);
+ post_code(0x3B);
-/* It's the time to set ctrl in sysinfo now; */
-printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
-fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+ /* It's the time to set ctrl in sysinfo now; */
+ printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-post_code(0x3D);
+ post_code(0x3D);
-//printk(BIOS_DEBUG, "enable_smbus()\n");
-// enable_smbus(); /* enable in sio_setup */
+// printk(BIOS_DEBUG, "enable_smbus()\n");
+// enable_smbus(); /* enable in sio_setup */
-post_code(0x40);
+ post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
- printk(BIOS_DEBUG, "raminit_amdmct()\n");
- raminit_amdmct(sysinfo);
+ printk(BIOS_DEBUG, "raminit_amdmct()\n");
+ raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
- cbmem_initialize_empty();
- post_code(0x41);
+ cbmem_initialize_empty();
+ post_code(0x41);
- amdmct_cbmem_store_info(sysinfo);
+ amdmct_cbmem_store_info(sysinfo);
timestamp_add_now(TS_END_ROMSTAGE);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x42); // Should never see this post code.
+ post_cache_as_ram(); /* BSP switch stack to ram, copy then execute CB. */
+ post_code(0x42); /* Should never see this post code. */
}
/**
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