[coreboot-gerrit] Patch merged into coreboot/master: 4d7d25f payloads/external/SeaBIOS: Allow setting buffers below 0xC0000
gerrit at coreboot.org
gerrit at coreboot.org
Fri Sep 12 23:16:31 CEST 2014
the following patch was just integrated into master:
commit 4d7d25f38abac4bcd3ea88a50b5f529f1e9ddb44
Author: Martin Roth <martin.roth at se-eng.com>
Date: Fri Jul 25 14:39:05 2014 -0600
payloads/external/SeaBIOS: Allow setting buffers below 0xC0000
Add the option to coreboot to set the SeaBIOS buffers below 0xC0000.
This is a requirement on the Intel Rangeley processor
because it is designed so that only the processor can write
the higher memory areas. This prevents USB and SATA from bus-mastering
into the buffers when they're set in the typical 0xE0000 area.
This will be set to Y unless defaulted to N by the mainboard or
chipset.
Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak
Change-Id: I15638605d1c66a2277d4b852796db89978551a34
Signed-off-by: Martin Roth <martin.roth at se-eng.com>
Reviewed-on: http://review.coreboot.org/6364
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
See http://review.coreboot.org/6364 for details.
-gerrit
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