[coreboot-gerrit] Patch merged into coreboot/master: 25ae602 rambi: switch MCLK from 19.2Mhz to 25Mhz

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 25ae602d2edb9426f94fe5fee26665d498f7fd9e
Author: Kein Yuan <kein.yuan at intel.com>
Date:   Fri Apr 4 15:15:14 2014 -0700

    rambi: switch MCLK from 19.2Mhz to 25Mhz
    
    With following settings
        1.Coreboot 25Mhz
        2.Maxim codec configured with MCLK=25Mhz
        2.I2C 400Khz fixed
        4.Including  Enable/Disable SHDN bit when LRCLK starts/Stops
        5.Removed PLL toggle workaround routine.
    audio playing is smooth before/after S3, no noise when recording so change
    MCLK from 19.2 back to 25Mhz.
    
    BUG=chrome-os-partner:26948
    BRANCH=firmware-rambi-5216
    TEST=test audio play and record on Rambi, works fine.
    
    Change-Id: I5602feb39721344feab837ff4a3a18309a47a6a6
    Signed-off-by: Kein Yuan <kein.yuan at intel.com>
    Reviewed-on: https://chromium-review.googlesource.com/193881
    Tested-by: Shawn Nematbakhsh <shawnn at chromium.org>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn at chromium.org>
    (cherry picked from commit bfe1d535aa2f20a32e163abeb99f3d657e2b43ab)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    Reviewed-on: http://review.coreboot.org/7219
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/7219 for details.

-gerrit