[coreboot-gerrit] New patch to review for coreboot: f2a0927 AGESA Hudson/Yangtze: Remove obsolete devicetree parameters

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7599

-gerrit

commit f2a09274d3a017ff828b466a8849a6368598e5b5
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Nov 21 08:40:43 2014 +0200

    AGESA Hudson/Yangtze: Remove obsolete devicetree parameters
    
    Change-Id: Ic6affae7e508f28b131c7d07191289f4fcbf2d74
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/mainboard/amd/parmer/devicetree.cb            | 1 -
 src/mainboard/amd/thatcher/devicetree.cb          | 1 -
 src/mainboard/asus/f2a85-m/devicetree.cb          | 1 -
 src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb | 1 -
 src/mainboard/lenovo/g505s/devicetree.cb          | 1 -
 src/southbridge/amd/agesa/hudson/chip.h           | 6 ------
 6 files changed, 11 deletions(-)

diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb
index 62b37e1..b63ba12 100644
--- a/src/mainboard/amd/parmer/devicetree.cb
+++ b/src/mainboard/amd/parmer/devicetree.cb
@@ -68,7 +68,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
 				device pci 15.1 off end # PCIe 1
 				device pci 15.2 off end # PCIe 2
 				device pci 15.3 off end # PCIe 3
-				register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				register "gpp_configuration" = "4"
 			end	#chip southbridge/amd/hudson
 
diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb
index 330ee6b..5fc4648 100644
--- a/src/mainboard/amd/thatcher/devicetree.cb
+++ b/src/mainboard/amd/thatcher/devicetree.cb
@@ -83,7 +83,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
 				device pci 15.1 off end # PCIe 1
 				device pci 15.2 off end # PCIe 2
 				device pci 15.3 off end # PCIe 3
-				register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				register "gpp_configuration" = "4"
 			end	#chip southbridge/amd/hudson
 
diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb
index 0396792..5158f19 100644
--- a/src/mainboard/asus/f2a85-m/devicetree.cb
+++ b/src/mainboard/asus/f2a85-m/devicetree.cb
@@ -116,7 +116,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
 				device pci 15.2 off end # unused
 				device pci 15.3 off end # unused
 
-				register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				register "gpp_configuration" = "4"
 			end	#chip southbridge/amd/hudson
 
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb
index 683d9ad..895437b 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb
+++ b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb
@@ -68,7 +68,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
 				device pci 15.1 off end # PCIe 1
 				device pci 15.2 off end # PCIe 2
 				device pci 15.3 off end # PCIe 3
-				register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				register "gpp_configuration" = "4"
 			end	#chip southbridge/amd/hudson
 
diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb
index 4dc4a14..3a518ab 100644
--- a/src/mainboard/lenovo/g505s/devicetree.cb
+++ b/src/mainboard/lenovo/g505s/devicetree.cb
@@ -72,7 +72,6 @@ chip northbridge/amd/agesa/family15rl/root_complex
 				device pci 15.1 off end # PCIe 1
 				device pci 15.2 off end # PCIe 2
 				device pci 15.3 off end # PCIe 3
-				register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				register "gpp_configuration" = "4"
 			end	#chip southbridge/amd/hudson
 
diff --git a/src/southbridge/amd/agesa/hudson/chip.h b/src/southbridge/amd/agesa/hudson/chip.h
index d5f14ff..21b8cd2 100644
--- a/src/southbridge/amd/agesa/hudson/chip.h
+++ b/src/southbridge/amd/agesa/hudson/chip.h
@@ -22,14 +22,8 @@
 
 struct southbridge_amd_agesa_hudson_config
 {
-	#if 1
-	u32 ide0_enable : 1;
-	u32 sata0_enable : 1;
-	u32 boot_switch_sata_ide : 1;
-	u32 hda_viddid;
 	u8  gpp_configuration;
 	u8  sd_mode;
-	#endif
 };
 
 #endif /* HUDSON_CHIP_H */