[coreboot-gerrit] Patch set updated for coreboot: 31e23e9 ACPI: Remove CBMEM TOC from GNVS
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Fri Nov 28 06:55:36 CET 2014
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7465
-gerrit
commit 31e23e9de7bd0c75c0ad7c8782c33487f1820608
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Sun Jun 15 14:28:23 2014 +0300
ACPI: Remove CBMEM TOC from GNVS
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM.
See commit a0b4a8d.
Change-Id: Iae82498ab729df5682d89e66bb9de96457e91619
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/intel/mohonpeak/acpi_tables.c | 3 ---
src/soc/intel/broadwell/broadwell/nvs.h | 2 +-
src/southbridge/intel/fsp_rangeley/nvs.h | 2 +-
3 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/mainboard/intel/mohonpeak/acpi_tables.c b/src/mainboard/intel/mohonpeak/acpi_tables.c
index b49da65..84f0083 100644
--- a/src/mainboard/intel/mohonpeak/acpi_tables.c
+++ b/src/mainboard/intel/mohonpeak/acpi_tables.c
@@ -54,9 +54,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 1;
gnvs->s5u1 = 1;
- /* CBMEM TOC */
- gnvs->cmem = (u32)get_cbmem_toc();
-
/* IGD Displays */
gnvs->ndid = 3;
gnvs->did[0] = 0x80000100;
diff --git a/src/soc/intel/broadwell/broadwell/nvs.h b/src/soc/intel/broadwell/broadwell/nvs.h
index df36a03..398e0a2 100644
--- a/src/soc/intel/broadwell/broadwell/nvs.h
+++ b/src/soc/intel/broadwell/broadwell/nvs.h
@@ -50,7 +50,7 @@ typedef struct {
u8 s33g; /* 0x16 - Enable 3G in S3 */
u8 lids; /* 0x17 - LID State */
u8 pwrs; /* 0x18 - AC Power State */
- u32 cmem; /* 0x19 - 0x1c - CBMEM TOC */
+ u32 obsolete_cmem; /* 0x19 - 0x1c - CBMEM TOC */
u32 cbmc; /* 0x1d - 0x20 - Coreboot Memory Console */
u32 pm1i; /* 0x21 - 0x24 - PM1 wake status bit */
u8 rsvd3[219];
diff --git a/src/southbridge/intel/fsp_rangeley/nvs.h b/src/southbridge/intel/fsp_rangeley/nvs.h
index 6578bbf..97362ea 100644
--- a/src/southbridge/intel/fsp_rangeley/nvs.h
+++ b/src/southbridge/intel/fsp_rangeley/nvs.h
@@ -71,7 +71,7 @@ typedef struct {
u8 s3u0; /* 0x35 - Enable USB0 in S3 */
u8 s3u1; /* 0x36 - Enable USB1 in S3 */
u8 s33g; /* 0x37 - Enable S3 in 3G */
- u32 cmem; /* 0x38 - CBMEM TOC */
+ u32 obsolete_cmem; /* 0x38 - CBMEM TOC */
/* Integrated Graphics Device */
u8 igds; /* 0x3c - IGD state */
u8 tlst; /* 0x3d - Display Toggle List Pointer */
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