[coreboot-gerrit] Patch set updated for coreboot: a7a7907 src/mainboard: Add experimental Asus M2N32-SLI-Deluxe support
Marcel Meißner (mm-meissner@gmx.de)
gerrit at coreboot.org
Wed Nov 26 18:09:52 CET 2014
Marcel Meißner (mm-meissner at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7546
-gerrit
commit a7a79078b9b81266ee2d8e433d686dc0da7fecce
Author: Marcel Meißner <mm-meissner at gmx.de>
Date: Fri Nov 21 10:12:10 2014 +0100
src/mainboard: Add experimental Asus M2N32-SLI-Deluxe support
reuse IT8716F S/IO and MCP55 southbridge code from asus/m2n-e
reuse northbridge code from gigabit/ma78g (both mainboards have an AM2+ socket)
Change-Id: I703daa20997cbcf6cf2d34f10dfb06db81db1fbf
Signed-off-by: Marcel Meißner <mm-meissner at gmx.de>
---
src/mainboard/asus/Kconfig | 3 +
src/mainboard/asus/m2n32_sli_deluxe/Kconfig | 66 +++++
src/mainboard/asus/m2n32_sli_deluxe/Makefile.inc | 21 ++
src/mainboard/asus/m2n32_sli_deluxe/board_info.txt | 6 +
src/mainboard/asus/m2n32_sli_deluxe/cmos.layout | 96 +++++++
src/mainboard/asus/m2n32_sli_deluxe/devicetree.cb | 102 ++++++++
src/mainboard/asus/m2n32_sli_deluxe/fanctl.c | 64 +++++
src/mainboard/asus/m2n32_sli_deluxe/get_bus_conf.c | 116 +++++++++
src/mainboard/asus/m2n32_sli_deluxe/mainboard.c | 84 +++++++
src/mainboard/asus/m2n32_sli_deluxe/mptable.c | 114 +++++++++
src/mainboard/asus/m2n32_sli_deluxe/resourcemap.c | 280 +++++++++++++++++++++
src/mainboard/asus/m2n32_sli_deluxe/romstage.c | 264 +++++++++++++++++++
12 files changed, 1216 insertions(+)
diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig
index edd8f5d..faf98bf 100644
--- a/src/mainboard/asus/Kconfig
+++ b/src/mainboard/asus/Kconfig
@@ -37,6 +37,8 @@ config BOARD_ASUS_K8V_X
bool "K8V-X"
config BOARD_ASUS_M2N_E
bool "M2N-E"
+config BOARD_ASUS_M2N32_SLI_DELUXE
+ bool "M2N32-SLI Deluxe"
config BOARD_ASUS_M2V
bool "M2V"
config BOARD_ASUS_M2V_MX_SE
@@ -77,6 +79,7 @@ source "src/mainboard/asus/f2a85-m/Kconfig"
source "src/mainboard/asus/f2a85-m_le/Kconfig"
source "src/mainboard/asus/k8v-x/Kconfig"
source "src/mainboard/asus/m2n-e/Kconfig"
+source "src/mainboard/asus/m2n32_sli_deluxe/Kconfig"
source "src/mainboard/asus/m2v/Kconfig"
source "src/mainboard/asus/m2v-mx_se/Kconfig"
source "src/mainboard/asus/m4a785-m/Kconfig"
diff --git a/src/mainboard/asus/m2n32_sli_deluxe/Kconfig b/src/mainboard/asus/m2n32_sli_deluxe/Kconfig
new file mode 100644
index 0000000..9f025fc
--- /dev/null
+++ b/src/mainboard/asus/m2n32_sli_deluxe/Kconfig
@@ -0,0 +1,66 @@
+if BOARD_ASUS_M2N32_SLI_DELUXE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_SOCKET_AM2R2
+ select DIMM_DDR2
+ select DIMM_REGISTERED
+ select NORTHBRIDGE_AMD_AMDFAM10
+ select SOUTHBRIDGE_NVIDIA_MCP55
+ select MCP55_USE_NIC
+ select MCP55_USE_AZA
+ select SUPERIO_ITE_IT8716F
+ select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ select LIFT_BSP_APIC_ID
+ select AMDMCT
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_1024
+ select ENABLE_APIC_EXT_ID
+ select GFXUMA
+ select FAM10_ALLOCATE_IO_RANGE
+
+config MAINBOARD_DIR
+ string
+ default asus/m2n32_sli_deluxe
+
+config APIC_ID_OFFSET
+ hex
+ default 0x0
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "M2N32-SLI Deluxe"
+
+config MAX_CPUS
+ int
+ default 4
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 1
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 1
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x1
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0x0
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config AMD_UCODE_PATCH_FILE
+ string
+ default "mc_patch_01000095.h"
+
+endif # BOARD_M2N32_SLI_DELUXE
diff --git a/src/mainboard/asus/m2n32_sli_deluxe/Makefile.inc b/src/mainboard/asus/m2n32_sli_deluxe/Makefile.inc
new file mode 100644
index 0000000..b8477db
--- /dev/null
+++ b/src/mainboard/asus/m2n32_sli_deluxe/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) += fanctl.c
diff --git a/src/mainboard/asus/m2n32_sli_deluxe/board_info.txt b/src/mainboard/asus/m2n32_sli_deluxe/board_info.txt
new file mode 100644
index 0000000..0afe04a
--- /dev/null
+++ b/src/mainboard/asus/m2n32_sli_deluxe/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: http://www.asus.com/Motherboards/M2N32SLI_DeluxeWireless_Edition/
+ROM package: PLCC
+ROM protocol: LPC
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/asus/m2n32_sli_deluxe/cmos.layout b/src/mainboard/asus/m2n32_sli_deluxe/cmos.layout
new file mode 100644
index 0000000..6565c88
--- /dev/null
+++ b/src/mainboard/asus/m2n32_sli_deluxe/cmos.layout
@@ -0,0 +1,96 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/asus/m2n32_sli_deluxe/devicetree.cb b/src/mainboard/asus/m2n32_sli_deluxe/devicetree.cb
new file mode 100644
index 0000000..0245617
--- /dev/null
+++ b/src/mainboard/asus/m2n32_sli_deluxe/devicetree.cb
@@ -0,0 +1,102 @@
+# sample config for m2n32_sli_deluxe
+chip northbridge/amd/amdfam10/root_complex
+ device cpu_cluster 0 on
+ chip cpu/amd/socket_AM2r2 #L1 and DDR2
+ device lapic 0 on end
+ end
+ end
+ device domain 0 on
+ subsystemid 0x1022 0x3060 inherit
+ chip northbridge/amd/amdfam10
+ device pci 18.0 on # northbridge
+ chip southbridge/nvidia/mcp55 # Southbridge
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/ite/it8716f # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off end # Com2 (N/A)
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ io 0x62 = 0x000
+ irq 0x70 = 7
+ drq 0x74 = 4
+ end
+ device pnp 2e.4 on # Environment controller
+ io 0x60 = 0x290
+ io 0x62 = 0x000
+ irq 0x70 = 0
+ end
+ device pnp 2e.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard IRQ
+ end
+ device pnp 2e.6 on # PS/2 mouse
+ irq 0x70 = 12 # PS/2 mouse IRQ
+ end
+ device pnp 2e.7 off # GPIO
+ io 0x60 = 0x0000 # SMI# Normal Run Access
+ io 0x62 = 0x800 # Simple I/O
+ io 0x64 = 0x0000 # Serial Flash I/F
+ end
+ device pnp 2e.8 off end # MIDI (N/A)
+ device pnp 2e.9 off end # Game port (N/A)
+ device pnp 2e.a off end # Consumer IR (N/A)
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/generic/generic # DIMM 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic # DIMM 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-1
+ device i2c 53 on end
+ end
+ end
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # IDE
+ device pci 5.0 on end # SATA 0
+ device pci 5.1 on end # SATA 1
+ device pci 5.2 on end # SATA 2
+ device pci 6.0 on end # PCI
+ device pci 6.1 on end # Azalia (HD Audio)
+ device pci 8.0 on end # NIC
+ device pci 9.0 off end # NIC (N/A)
+ device pci a.0 on end # PCI E 5 (PCIEX4)
+ device pci b.0 off end # PCI E 4
+ device pci c.0 on end # PCI E 3 (PCIEX1_2)
+ device pci d.0 on end # PCI E 2 (PCIEX1_1)
+ device pci e.0 off end # PCI E 1
+ device pci f.0 on end # PCI E 0 (PCIEX16_1)
+ register "ide0_enable" = "1" # Primary IDE
+ register "ide1_enable" = "0" # Secondary IDE (N/A)
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ end
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ # device pci 00.5 on end
+ end
+ end #domain
+#for node 32 to node 63
+end
diff --git a/src/mainboard/asus/m2n32_sli_deluxe/fanctl.c b/src/mainboard/asus/m2n32_sli_deluxe/fanctl.c
new file mode 100644
index 0000000..bcee1d3
--- /dev/null
+++ b/src/mainboard/asus/m2n32_sli_deluxe/fanctl.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The ASUS M2N-E has 6 different fans, connected to two different chips:
+ * - ITE IT8716F: fan1 = CPU_FAN, fan2 = CHA_FAN1, fan3 = PWR_FAN1
+ * - Analog Devices ADT7475: fan1 = CHA_FAN4, fan2 = CHA_FAN2, fan3 = CHA_FAN3
+ */
+
+#include <arch/io.h>
+#include <stdlib.h>
+#include <superio/ite/it8716f/it8716f.h>
+
+static void write_index(u16 port, u8 reg, u8 value)
+{
+ outb(reg, port);
+ outb(value, port + 1);
+}
+
+static const struct {
+ u8 index;
+ u8 value;
+} sequence[] = {
+ /* Enable startup of monitoring operations. */
+ { 0x00, 0x11},
+ /* Polarity active-high, PWM frequency 23.43KHz, activate fans 1-3. */
+ { 0x14, 0xd7},
+ /* Set the correct sensor types. TMPIN1: diode, TMPIN2/3: resistor. */
+ { 0x51, 0x31},
+ /* Fan1 (CPU_FAN) is software-controlled. */
+ { 0x15, 0x7f},
+ /* Fan2 (CHA_FAN1) is software-controlled. */
+ { 0x16, 0x7f},
+ /* Fan3 (PWR_FAN1) is software-controlled. */
+ { 0x17, 0x7f},
+ /* Enable fan1/2/3, select "on/off mode" for all of them. */
+ { 0x13, 0x70},
+};
+
+/* Called from src/ite/it8716f/superio.c. */
+void init_ec(u16 base)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(sequence); i++)
+ write_index(base, sequence[i].index, sequence[i].value);
+}
diff --git a/src/mainboard/asus/m2n32_sli_deluxe/get_bus_conf.c b/src/mainboard/asus/m2n32_sli_deluxe/get_bus_conf.c
new file mode 100644
index 0000000..47342fb
--- /dev/null
+++ b/src/mainboard/asus/m2n32_sli_deluxe/get_bus_conf.c
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#if CONFIG_LOGICAL_CPUS
+#include <cpu/amd/multicore.h>
+#endif
+
+#include <cpu/amd/amdfam10_sysconf.h>
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+* and acpi_tables busnum is default.
+*/
+u8 bus_rs780[11];
+u8 bus_sb700[2];
+u32 apicid_sb700;
+
+/*
+* Here you only need to set value in pci1234 for HT-IO that could be installed or not
+* You may need to preset pci1234 for HTIO board,
+* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+*/
+u32 pci1234x[] = {
+ 0x0000ff0,
+};
+
+/*
+* HT Chain device num, actually it is unit id base of every ht device in chain,
+* assume every chain only have 4 ht device at most
+*/
+u32 hcdnx[] = {
+ 0x20202020,
+};
+
+u32 sbdn_rs780;
+u32 sbdn_sb700;
+
+extern void get_pci1234(void);
+
+static u32 get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+ u32 apicid_base;
+ device_t dev;
+ int i;
+
+ if (get_bus_conf_done == 1)
+ return; /* do it only once */
+ get_bus_conf_done = 1;
+
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+ for (i = 0; i < sysconf.hc_possible_num; i++) {
+ sysconf.pci1234[i] = pci1234x[i];
+ sysconf.hcdn[i] = hcdnx[i];
+ }
+
+ get_pci1234();
+
+ sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
+ sbdn_rs780 = sysconf.sbdn;
+ sbdn_sb700 = 0;
+
+ for (i = 0; i < 2; i++) {
+ bus_sb700[i] = 0;
+ }
+ for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
+ bus_rs780[i] = 0;
+ }
+
+ bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+ bus_sb700[0] = bus_rs780[0];
+
+ /* sb700 */
+ dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
+ if (dev) {
+ bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ }
+
+ /* rs780 */
+ for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
+ dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
+ if (dev) {
+ bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ }
+ }
+
+ /* I/O APICs: APIC ID Version State Address */
+#if CONFIG_LOGICAL_CPUS
+ apicid_base = get_apicid_base(1);
+#else
+ apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+ apicid_sb700 = apicid_base + 0;
+}
diff --git a/src/mainboard/asus/m2n32_sli_deluxe/mainboard.c b/src/mainboard/asus/m2n32_sli_deluxe/mainboard.c
new file mode 100644
index 0000000..49df0c2
--- /dev/null
+++ b/src/mainboard/asus/m2n32_sli_deluxe/mainboard.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Wang Qing Pei <wangqingpei at gmail.com>
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+u8 is_dev3_present(void);
+/*
+ * ma78gm-us2h uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
+ * pull it up before training the slot.
+ ***/
+void set_pcie_dereset()
+{
+ u16 word;
+ device_t sm_dev;
+ /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ word = pci_read_config16(sm_dev, 0xA8);
+ word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */
+ word &= ~((1 << 8) | (1 << 10));
+ pci_write_config16(sm_dev, 0xA8, word);
+}
+
+void set_pcie_reset()
+{
+ u16 word;
+ device_t sm_dev;
+ /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ word = pci_read_config16(sm_dev, 0xA8);
+ word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
+ word &= ~((1 << 8) | (1 << 10));
+ pci_write_config16(sm_dev, 0xA8, word);
+}
+
+
+u8 is_dev3_present(void)
+{
+ return 0;
+}
+
+/*************************************************
+* enable the dedicated function in board.
+* This function called early than rs780_enable.
+*************************************************/
+static void mainboard_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ /* get_ide_dma66(); */
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/asus/m2n32_sli_deluxe/mptable.c b/src/mainboard/asus/m2n32_sli_deluxe/mptable.c
new file mode 100644
index 0000000..11426c2
--- /dev/null
+++ b/src/mainboard/asus/m2n32_sli_deluxe/mptable.c
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+extern u8 bus_rs780[11];
+extern u8 bus_sb700[2];
+
+extern u32 apicid_sb700;
+
+extern u32 sbdn_rs780;
+extern u32 sbdn_sb700;
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+
+ smp_write_processors(mc);
+
+ get_bus_conf();
+
+ mptable_write_buses(mc, NULL, &bus_isa);
+
+ /* I/O APICs: APIC ID Version State Address */
+ {
+ device_t dev;
+ u32 dword;
+ u8 byte;
+
+ dev =
+ dev_find_slot(bus_sb700[0],
+ PCI_DEVFN(sbdn_sb700 + 0x14, 0));
+ if (dev) {
+ dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+
+ /* Initialize interrupt mapping */
+ /* aza */
+ byte = pci_read_config8(dev, 0x63);
+ byte &= 0xf8;
+ byte |= 0; /* 0: INTA, ...., 7: INTH */
+ pci_write_config8(dev, 0x63, byte);
+
+ /* SATA */
+ dword = pci_read_config32(dev, 0xac);
+ dword &= ~(7 << 26);
+ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
+ /* dword |= 1<<22; PIC and APIC co exists */
+ pci_write_config32(dev, 0xac, dword);
+
+ /*
+ * 00:12.0: PROG SATA : INT F
+ * 00:13.0: INTA USB_0
+ * 00:13.1: INTB USB_1
+ * 00:13.2: INTC USB_2
+ * 00:13.3: INTD USB_3
+ * 00:13.4: INTC USB_4
+ * 00:13.5: INTD USB2
+ * 00:14.1: INTA IDE
+ * 00:14.2: Prog HDA : INT E
+ * 00:14.5: INTB ACI
+ * 00:14.6: INTB MCI
+ */
+ }
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+ mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/asus/m2n32_sli_deluxe/resourcemap.c b/src/mainboard/asus/m2n32_sli_deluxe/resourcemap.c
new file mode 100644
index 0000000..fc92f62
--- /dev/null
+++ b/src/mainboard/asus/m2n32_sli_deluxe/resourcemap.c
@@ -0,0 +1,280 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+
+static void setup_mb_resource_map(void)
+{
+ static const unsigned int register_values[] = {
+ /* Careful set limit registers before base registers which contain the enables */
+ /* DRAM Limit i Registers
+ * F1:0x44 i = 0
+ * F1:0x4C i = 1
+ * F1:0x54 i = 2
+ * F1:0x5C i = 3
+ * F1:0x64 i = 4
+ * F1:0x6C i = 5
+ * F1:0x74 i = 6
+ * F1:0x7C i = 7
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 7: 3] Reserved
+ * [10: 8] Interleave select
+ * specifies the values of A[14:12] to use with interleave enable.
+ * [15:11] Reserved
+ * [31:16] DRAM Limit Address i Bits 39-24
+ * This field defines the upper address bits of a 40 bit address
+ * that define the end of the DRAM region.
+ */
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+ /* DRAM Base i Registers
+ * F1:0x40 i = 0
+ * F1:0x48 i = 1
+ * F1:0x50 i = 2
+ * F1:0x58 i = 3
+ * F1:0x60 i = 4
+ * F1:0x68 i = 5
+ * F1:0x70 i = 6
+ * F1:0x78 i = 7
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 7: 2] Reserved
+ * [10: 8] Interleave Enable
+ * 000 = No interleave
+ * 001 = Interleave on A[12] (2 nodes)
+ * 010 = reserved
+ * 011 = Interleave on A[12] and A[14] (4 nodes)
+ * 100 = reserved
+ * 101 = reserved
+ * 110 = reserved
+ * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+ * [15:11] Reserved
+ * [13:16] DRAM Base Address i Bits 39-24
+ * This field defines the upper address bits of a 40-bit address
+ * that define the start of the DRAM region.
+ */
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+ /* Memory-Mapped I/O Limit i Registers
+ * F1:0x84 i = 0
+ * F1:0x8C i = 1
+ * F1:0x94 i = 2
+ * F1:0x9C i = 3
+ * F1:0xA4 i = 4
+ * F1:0xAC i = 5
+ * F1:0xB4 i = 6
+ * F1:0xBC i = 7
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 3: 3] Reserved
+ * [ 5: 4] Destination Link ID
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 = Reserved
+ * [ 6: 6] Reserved
+ * [ 7: 7] Non-Posted
+ * 0 = CPU writes may be posted
+ * 1 = CPU writes must be non-posted
+ * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+ * This field defines the upp adddress bits of a 40-bit address that
+ * defines the end of a memory-mapped I/O region n
+ */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+ /* Memory-Mapped I/O Base i Registers
+ * F1:0x80 i = 0
+ * F1:0x88 i = 1
+ * F1:0x90 i = 2
+ * F1:0x98 i = 3
+ * F1:0xA0 i = 4
+ * F1:0xA8 i = 5
+ * F1:0xB0 i = 6
+ * F1:0xB8 i = 7
+ * [ 0: 0] Read Enable
+ * 0 = Reads disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes disabled
+ * 1 = Writes Enabled
+ * [ 2: 2] Cpu Disable
+ * 0 = Cpu can use this I/O range
+ * 1 = Cpu requests do not use this I/O range
+ * [ 3: 3] Lock
+ * 0 = base/limit registers i are read/write
+ * 1 = base/limit registers i are read-only
+ * [ 7: 4] Reserved
+ * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+ * This field defines the upper address bits of a 40bit address
+ * that defines the start of memory-mapped I/O region i
+ */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+ /* PCI I/O Limit i Registers
+ * F1:0xC4 i = 0
+ * F1:0xCC i = 1
+ * F1:0xD4 i = 2
+ * F1:0xDC i = 3
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 3: 3] Reserved
+ * [ 5: 4] Destination Link ID
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 = reserved
+ * [11: 6] Reserved
+ * [24:12] PCI I/O Limit Address i
+ * This field defines the end of PCI I/O region n
+ * [31:25] Reserved
+ */
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+ /* PCI I/O Base i Registers
+ * F1:0xC0 i = 0
+ * F1:0xC8 i = 1
+ * F1:0xD0 i = 2
+ * F1:0xD8 i = 3
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 3: 2] Reserved
+ * [ 4: 4] VGA Enable
+ * 0 = VGA matches Disabled
+ * 1 = matches all address < 64K and where A[9:0] is in the
+ * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+ * [ 5: 5] ISA Enable
+ * 0 = ISA matches Disabled
+ * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+ * from matching agains this base/limit pair
+ * [11: 6] Reserved
+ * [24:12] PCI I/O Base i
+ * This field defines the start of PCI I/O region n
+ * [31:25] Reserved
+ */
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+ /* Config Base and Limit i Registers
+ * F1:0xE0 i = 0
+ * F1:0xE4 i = 1
+ * F1:0xE8 i = 2
+ * F1:0xEC i = 3
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 2: 2] Device Number Compare Enable
+ * 0 = The ranges are based on bus number
+ * 1 = The ranges are ranges of devices on bus 0
+ * [ 3: 3] Reserved
+ * [ 6: 4] Destination Node
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 7: 7] Reserved
+ * [ 9: 8] Destination Link
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 - Reserved
+ * [15:10] Reserved
+ * [23:16] Bus Number Base i
+ * This field defines the lowest bus number in configuration region i
+ * [31:24] Bus Number Limit i
+ * This field defines the highest bus number in configuration regin i
+ */
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+ };
+
+ int max;
+ max = ARRAY_SIZE(register_values);
+ setup_resource_map(register_values, max);
+}
diff --git a/src/mainboard/asus/m2n32_sli_deluxe/romstage.c b/src/mainboard/asus/m2n32_sli_deluxe/romstage.c
new file mode 100644
index 0000000..6151122
--- /dev/null
+++ b/src/mainboard/asus/m2n32_sli_deluxe/romstage.c
@@ -0,0 +1,264 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+//#define SYSTEM_TYPE 0 /* SERVER */
+#define SYSTEM_TYPE 1 /* DESKTOP */
+//#define SYSTEM_TYPE 2 /* MOBILE */
+
+//used by incoherent_ht
+#define FAM10_SCAN_PCI_BUS 0
+#define FAM10_ALLOCATE_IO_RANGE 0
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/amd/model_10xxx_rev.h>
+#include "northbridge/amd/amdfam10/raminit.h"
+#include "northbridge/amd/amdfam10/amdfam10.h"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
+#include "lib/delay.c"
+#include <lib.h>
+#include "cpu/x86/lapic.h"
+#include "northbridge/amd/amdfam10/reset_test.c"
+#include <console/loglevel.h>
+#include "cpu/x86/bist.h"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8716f/it8716f.h>
+#include <cpu/amd/mtrr.h>
+#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
+#include "northbridge/amd/amdfam10/debug.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
+#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdfam10/amdfam10.h"
+#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
+#include "northbridge/amd/amdfam10/pci.c"
+#include "resourcemap.c"
+#include "cpu/amd/quadcore/quadcore.c"
+#include "cpu/amd/microcode.h"
+
+#include "cpu/amd/model_10xxx/init_cpus.c"
+#include "northbridge/amd/amdfam10/early_ht.c"
+#include <spd.h>
+
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
+
+static void sio_setup(void)
+{
+ u8 byte;
+ u32 dword;
+ device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */
+
+ /* Subject decoding */
+ byte = pci_read_config8(dev, 0x7b);
+ byte |= (1 << 5);
+ pci_write_config8(dev, 0x7b, byte);
+
+ /* LPC Positive Decode 0 */
+ dword = pci_read_config32(dev, 0xa0);
+ dword |= (1 << 0); /* COM1 */
+ pci_write_config32(dev, 0xa0, dword);
+}
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
+ struct sys_info *sysinfo = &sysinfo_car;
+ int needs_reset = 0;
+ unsigned bsp_apicid = 0, val;
+ msr_t msr;
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ /* Allow the HT devices to be found. */
+ set_bsp_node_CHtExtNodeCfgEn();
+ enumerate_ht_chain();
+ sio_setup();
+ }
+
+ post_code(0x30);
+
+ if (bist == 0) {
+ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+ }
+
+ post_code(0x32);
+
+ ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ setup_mb_resource_map();
+ report_bist_failure(bist);
+ console_init();
+
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);
+ printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid);
+
+ /* In BSP so could hold all AP until sysinfo is in RAM. */
+ set_sysinfo_in_ram(0);
+
+ update_microcode(val);
+
+ post_code(0x33);
+
+ cpuSetAMDMSR();
+ post_code(0x34);
+
+ amd_ht_init(sysinfo);
+ post_code(0x35);
+
+ finalize_node_setup(sysinfo);
+ /* Setup any mainboard PCI settings etc. */
+ setup_mb_resource_map();
+ post_code(0x36);
+
+ wait_all_core0_started();
+
+#if CONFIG_LOGICAL_CPUS
+ /*
+ * It is said that we should start core1 after all core0 launched
+ * becase optimize_link_coherent_ht is moved out from
+ * setup_coherent_ht_domain, so here need to make sure last core0 is
+ * started, esp for two way system (there may be APIC ID conflicts in
+ * that case).
+ */
+ start_other_cores();
+ post_code(0x37);
+ wait_all_other_cores_started(bsp_apicid);
+#endif
+
+ post_code(0x38);
+#if CONFIG_SET_FIDVID
+ msr = rdmsr(0xc0010071);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
+
+ /* FIXME: The sb fid change may survive the warm reset and only
+ need to be done once.*/
+ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+ post_code(0x39);
+
+ if (!warm_reset_detect(0)) { // BSP is node 0
+ init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
+ } else {
+ init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ }
+
+ post_code(0x3A);
+
+ /* show final fid and vid */
+ msr=rdmsr(0xc0010071);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
+#endif
+
+
+ /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+ if (!warm_reset_detect(0)) {
+ print_info("...WARM RESET...\n\n\n");
+ soft_reset();
+ die("After soft_reset_x - shouldn't see this message!!!\n");
+ }
+ post_code(0x3B);
+
+ /* It's the time to set ctrl in sysinfo now; */
+
+ post_code(0x42);
+ init_timer(); /* Need to use TMICT to synconize FID/VID. */
+
+ needs_reset |= mcp55_early_setup_x();
+
+ /*
+ * FIDVID change will issue one LDTSTOP and the HT change will be
+ * effective too.
+ */
+ if (needs_reset) {
+ print_info("ht reset -\n");
+ soft_reset();
+ }
+ allow_all_aps_stop(bsp_apicid);
+
+ printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+ post_code(0x40);
+
+// die("Die Before MCT init.");
+
+ printk(BIOS_DEBUG, "raminit_amdmct()\n");
+ raminit_amdmct(sysinfo);
+ post_code(0x41);
+
+ enable_smbus();
+ post_code(0x42);
+ /* BSP switch stack to RAM and copy sysinfo RAM now. */
+ post_cache_as_ram();
+ post_code(0x43);
+}
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ * This routine is called every time a non-coherent chain is processed.
+ * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ * swap list. The first part of the list controls the BUID assignment and the
+ * second part of the list provides the device to device linking. Device orientation
+ * can be detected automatically, or explicitly. See documentation for more details.
+ *
+ * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ * based on each device's unit count.
+ *
+ * Parameters:
+ * @param[in] u8 node = The node on which this chain is located
+ * @param[in] u8 link = The link on the host for this chain
+ * @param[out] u8** list = supply a pointer to a list
+ * @param[out] BOOL result = true to use a manual list
+ * false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+ static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+ /* If the BUID was adjusted in early_ht we need to do the manual override */
+ if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+ printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+ if ((node == 0) && (link == 0)) { /* BSP SB link */
+ *List = swaplist;
+ return 1;
+ }
+ }
+
+ return 0;
+}
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