[coreboot-gerrit] Patch merged into coreboot/master: 33b535f sandy/ivy/nehalem: Remerge interrupt handling

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 33b535f15ded011c92cd1757408a3453a55b44bd
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date:   Sun Oct 19 10:13:14 2014 +0200

    sandy/ivy/nehalem: Remerge interrupt handling
    
    On those chipsets the pins are just a legacy concept. Real interrupts are
    messages on corresponding busses or some internal logic of chipset.
    Hence interrupt routing isn't anymore board-specific (dependent on layout) but
    depends only on configuration.
    Rather than attempting to sync real config, ACPI and legacy descriptors, just
    use the same interrupt routing per chipset covering all possible devices.
    
    The only part which remains board-specific are LPC and PCI interrupts.
    
    Interrupt balancing may suffer from such merge but:
    a) Doesn't seem to be the case of this map on current systems
    b) Almost all OS use MSI nowadays bypassing this stuff completely
    c) If we want a good balancing we need to take into account that e.g.
       wlan card may be placed in a different slot and so would require complicated
       balancing on runtime. It's difficult to maintain with almost no benefit.
    
    Change-Id: I9f63d1d338c5587ebac7a52093e5b924f6e5ca2d
    Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
    Reviewed-on: http://review.coreboot.org/7130
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki at gmail.com>


See http://review.coreboot.org/7130 for details.

-gerrit