[coreboot-gerrit] New patch to review for coreboot: e1d4fa1 mainboard/lenovo/g505s: New port - NOTYET -
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Sun Nov 23 06:52:43 CET 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7560
-gerrit
commit e1d4fa126860dcadb2e4d06fafe42808b8eb51d6
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Sun Nov 23 16:50:42 2014 +1100
mainboard/lenovo/g505s: New port - NOTYET -
Change-Id: I5d05d1b31400fdb9e41c2e011c5b0bf9986fe970
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/mainboard/lenovo/Kconfig | 6 +
src/mainboard/lenovo/g505s/BiosCallOuts.c | 221 +++++++
src/mainboard/lenovo/g505s/Kconfig | 76 +++
src/mainboard/lenovo/g505s/Makefile.inc | 31 +
src/mainboard/lenovo/g505s/OptionsIds.h | 67 +++
src/mainboard/lenovo/g505s/PlatformGnbPcie.c | 198 +++++++
.../lenovo/g505s/PlatformGnbPcieComplex.h | 31 +
src/mainboard/lenovo/g505s/acpi/AmdImc.asl | 97 ++++
src/mainboard/lenovo/g505s/acpi/ec.asl | 10 +
src/mainboard/lenovo/g505s/acpi/gpe.asl | 80 +++
src/mainboard/lenovo/g505s/acpi/mainboard.asl | 129 +++++
src/mainboard/lenovo/g505s/acpi/routing.asl | 324 +++++++++++
src/mainboard/lenovo/g505s/acpi/sata.asl | 20 +
src/mainboard/lenovo/g505s/acpi/si.asl | 26 +
src/mainboard/lenovo/g505s/acpi/sleep.asl | 103 ++++
src/mainboard/lenovo/g505s/acpi/superio.asl | 20 +
src/mainboard/lenovo/g505s/acpi/thermal.asl | 20 +
src/mainboard/lenovo/g505s/acpi/usb_oc.asl | 31 +
src/mainboard/lenovo/g505s/acpi_tables.c | 280 +++++++++
src/mainboard/lenovo/g505s/agesawrapper.c | 641 +++++++++++++++++++++
src/mainboard/lenovo/g505s/agesawrapper.h | 60 ++
src/mainboard/lenovo/g505s/board_info.txt | 5 +
src/mainboard/lenovo/g505s/buildOpts.c | 442 ++++++++++++++
src/mainboard/lenovo/g505s/cmos.layout | 114 ++++
src/mainboard/lenovo/g505s/devicetree.cb | 94 +++
src/mainboard/lenovo/g505s/dsdt.asl | 91 +++
src/mainboard/lenovo/g505s/ec.c | 36 ++
src/mainboard/lenovo/g505s/ec.h | 15 +
src/mainboard/lenovo/g505s/irq_tables.c | 107 ++++
src/mainboard/lenovo/g505s/mainboard.c | 60 ++
src/mainboard/lenovo/g505s/mainboard.h | 25 +
src/mainboard/lenovo/g505s/mainboard_smi.c | 107 ++++
src/mainboard/lenovo/g505s/mptable.c | 195 +++++++
src/mainboard/lenovo/g505s/romstage.c | 90 +++
34 files changed, 3852 insertions(+)
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index d13fa86..2f1fac7 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -50,6 +50,11 @@ config BOARD_LENOVO_T60
Thinkpad T60p (Model 2007)
+config BOARD_LENOVO_G505S
+ bool "AMD G505s"
+ help
+ Lenovo G505s
+
endchoice
source "src/mainboard/lenovo/x60/Kconfig"
@@ -60,6 +65,7 @@ source "src/mainboard/lenovo/x230/Kconfig"
source "src/mainboard/lenovo/t520/Kconfig"
source "src/mainboard/lenovo/t530/Kconfig"
source "src/mainboard/lenovo/t60/Kconfig"
+source "src/mainboard/lenovo/g505s/Kconfig"
config MAINBOARD_VENDOR
string
diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c
new file mode 100644
index 0000000..5373d90
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c
@@ -0,0 +1,221 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include "OptionsIds.h"
+
+#include <cbfs.h>
+#include <southbridge/amd/agesa/hudson/imc.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
+#include <stdlib.h>
+
+static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
+ {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
+ {AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
+ {AGESA_DO_RESET, agesa_Reset },
+ {AGESA_READ_SPD, agesa_ReadSpd },
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+ {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
+ {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+/**
+ * AMD Parmer Platform ALC272 Verb Table
+ */
+static const CODEC_ENTRY Parmer_Alc272_VerbTbl[] = {
+ {0x11, 0x411111F0},
+ {0x12, 0x411111F0},
+ {0x13, 0x411111F0},
+ {0x14, 0x411111F0},
+ {0x15, 0x411111F0},
+ {0x16, 0x411111F0},
+ {0x17, 0x411111F0},
+ {0x18, 0x01a19840},
+ {0x19, 0x411111F0},
+ {0x1a, 0x01813030},
+ {0x1b, 0x411111F0},
+ {0x1d, 0x40130605},
+ {0x1e, 0x01441120},
+ {0x21, 0x01211010},
+ {0xff, 0xffffffff}
+};
+
+static const CODEC_TBL_LIST CodecTableList[] =
+{
+ {0x10ec0272, (CODEC_ENTRY*)&Parmer_Alc272_VerbTbl[0]},
+ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
+};
+
+#define FAN_INPUT_INTERNAL_DIODE 0
+#define FAN_INPUT_TEMP0 1
+#define FAN_INPUT_TEMP1 2
+#define FAN_INPUT_TEMP2 3
+#define FAN_INPUT_TEMP3 4
+#define FAN_INPUT_TEMP0_FILTER 5
+#define FAN_INPUT_ZERO 6
+#define FAN_INPUT_DISABLED 7
+
+#define FAN_AUTOMODE (1 << 0)
+#define FAN_LINEARMODE (1 << 1)
+#define FAN_STEPMODE ~(1 << 1)
+#define FAN_POLARITY_HIGH (1 << 2)
+#define FAN_POLARITY_LOW ~(1 << 2)
+
+/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
+#define FREQ_28KHZ 0x0
+#define FREQ_25KHZ 0x1
+#define FREQ_23KHZ 0x2
+#define FREQ_21KHZ 0x3
+#define FREQ_29KHZ 0x4
+#define FREQ_18KHZ 0x5
+#define FREQ_100HZ 0xF7
+#define FREQ_87HZ 0xF8
+#define FREQ_58HZ 0xF9
+#define FREQ_44HZ 0xFA
+#define FREQ_35HZ 0xFB
+#define FREQ_29HZ 0xFC
+#define FREQ_22HZ 0xFD
+#define FREQ_14HZ 0xFE
+#define FREQ_11HZ 0xFF
+
+/* Parmer Hardware Monitor Fan Control
+ * Hardware limitation:
+ * HWM failed to read the input temperture vi I2C,
+ * if other software switch the I2C switch by mistake or intention.
+ * We recommend to using IMC to control Fans, instead of HWM.
+ */
+static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
+{
+ /* Enable IMC fan control. the recommand way */
+#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
+
+ imc_reg_init();
+
+ /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
+ FchParams->Hwm.HwMonitorEnable = TRUE;
+ FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */
+
+ FchParams->Imc.ImcEnable = TRUE;
+ FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+
+ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
+
+ /* Thermal Zone Parameter */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x02;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
+
+ /* IMC Fan Policy temperature thresholds */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
+
+ /* IMC Fan Policy PWM Settings */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
+
+ FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
+
+ /* NOTE:
+ * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
+ * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it.
+ * so we remove it from AGESA code. Please Seee FchInitLateHwm.
+ */
+
+#else /* HWM fan control, the way not recommand */
+ FchParams->Imc.ImcEnable = FALSE;
+ FchParams->Hwm.HwMonitorEnable = TRUE;
+ FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */
+
+#endif /* CONFIG_HUDSON_IMC_FWM */
+}
+
+/**
+ * Fch Oem setting callback
+ *
+ * Configure platform specific Hudson device,
+ * such Azalia, SATA, IMC etc.
+ */
+static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
+{
+ AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
+
+ if (StdHeader->Func == AMD_INIT_RESET) {
+ FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
+ printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
+ //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+ FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams_reset->FchReset.Xhci1Enable = FALSE;
+ } else if (StdHeader->Func == AMD_INIT_ENV) {
+ FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
+ printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
+
+ /* Azalia Controller OEM Codec Table Pointer */
+ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
+ /* Azalia Controller Front Panel OEM Table Pointer */
+
+ /* Fan Control */
+ oem_fan_control(FchParams_env);
+
+ /* XHCI configuration */
+ FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams_env->Usb.Xhci1Enable = FALSE;
+
+ /* sata configuration */
+ }
+ printk(BIOS_DEBUG, "Done\n");
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig
new file mode 100644
index 0000000..5f51392
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/Kconfig
@@ -0,0 +1,76 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+if BOARD_LENOVO_G505S
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select SYSTEM_TYPE_LAPTOP
+ select CPU_AMD_AGESA_FAMILY15_RL
+ select NORTHBRIDGE_AMD_AGESA_FAMILY15_RL
+ select SOUTHBRIDGE_AMD_AGESA_HUDSON
+ select EC_COMPAL_ENE932
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_SMI_HANDLER
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_4096
+ select GFXUMA
+ select UDELAY_LAPIC
+ select USBDEBUG_IN_ROMSTAGE
+
+config MAINBOARD_DIR
+ string
+ default lenovo/g505s
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "LENOVO G505S"
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 4
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS_ID
+ string
+ default "1002,9900"
+
+config HUDSON_LEGACY_FREE
+ bool
+ default y
+
+endif
diff --git a/src/mainboard/lenovo/g505s/Makefile.inc b/src/mainboard/lenovo/g505s/Makefile.inc
new file mode 100644
index 0000000..7039c72
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/Makefile.inc
@@ -0,0 +1,31 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+romstage-y += buildOpts.c
+romstage-y += agesawrapper.c
+romstage-y += BiosCallOuts.c
+romstage-y += PlatformGnbPcie.c
+
+ramstage-y += buildOpts.c
+ramstage-y += agesawrapper.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += PlatformGnbPcie.c
+ramstage-y += ec.c
+
+smm-y += mainboard_smi.c
diff --git a/src/mainboard/lenovo/g505s/OptionsIds.h b/src/mainboard/lenovo/g505s/OptionsIds.h
new file mode 100644
index 0000000..e006441
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/OptionsIds.h
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+//#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+//#define IDSOPT_PERF_ANALYSIS TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/lenovo/g505s/PlatformGnbPcie.c b/src/mainboard/lenovo/g505s/PlatformGnbPcie.c
new file mode 100644
index 0000000..de046ac
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/PlatformGnbPcie.c
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "PlatformGnbPcieComplex.h"
+
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
+
+#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
+
+/*
+ * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
+ *
+ * Lane Id
+ * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
+ * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
+ * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
+ * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
+ * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
+ * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
+ * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
+ * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
+ * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
+ * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
+ * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
+ * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
+ * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
+ * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
+ * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
+ * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
+ * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
+ * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
+ * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
+ * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
+ * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
+ * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
+ * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
+ * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
+ * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
+ * 25 DP0_TX[P,N]1
+ * 26 DP0_TX[P,N]2
+ * 27 DP0_TX[P,N]3
+ * 28 DP1_TX[P,N]0
+ * 29 DP1_TX[P,N]1
+ * 30 DP1_TX[P,N]2
+ * 31 DP1_TX[P,N]3
+ * 32 DP2_TX[P,N]0
+ * 33 DP2_TX[P,N]1
+ * 34 DP2_TX[P,N]2
+ * 35 DP2_TX[P,N]3
+ * 36 DP2_TX[P,N]4
+ * 37 DP2_TX[P,N]5
+ * 38 DP2_TX[P,N]6
+ */
+
+static const PCIe_PORT_DESCRIPTOR PortList [] = {
+ /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */
+ {
+ 0, /* Descriptor flags */
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ },
+ /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
+ {
+ 0, /* Descriptor flags */
+ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23),
+ PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ },
+
+ /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
+ {
+ 0, /* Descriptor flags */
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ },
+
+ /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
+ {
+ 0, /* Descriptor flags */
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ },
+
+ /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
+ {
+ 0, /* Descriptor flags */
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ },
+
+ /* PCIe port, Lanes 7, PCI Device Number 7, LAN */
+ {
+ 0, /* Descriptor flags */
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ },
+
+ /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
+ {
+ DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ },
+};
+
+static const PCIe_DDI_DESCRIPTOR DdiList [] = {
+ /* DP0 to HDMI0/DP */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+ },
+ /* DP1 to FCH */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
+ },
+ /* DP2 to HDMI1/DP */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35),
+ /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) */
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3)
+ },
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * OemCustomizeInitEarly
+ *
+ * Description:
+ * This stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
+ *
+ * Parameters:
+ * @param[in] **PeiServices
+ * @param[in] *InitEarly
+ *
+ * @retval VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ )
+{
+ AGESA_STATUS Status;
+ PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
+
+ ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+ /* GNB PCIe topology Porting */
+
+ /* */
+ /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
+ /* */
+ AllocHeapParams.RequestedBufferSize = sizeof(PCIe_COMPLEX_DESCRIPTOR);
+
+ AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
+ AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+ Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
+ if ( Status!= AGESA_SUCCESS) {
+ /* Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR */
+ ASSERT(FALSE);
+ return;
+ }
+
+ PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+ LibAmdMemFill (PcieComplexListPtr,
+ 0,
+ sizeof(PCIe_COMPLEX_DESCRIPTOR),
+ &InitEarly->StdHeader);
+
+ PcieComplexListPtr->Flags = DESCRIPTOR_TERMINATE_LIST;
+ PcieComplexListPtr->SocketId = 0;
+ PcieComplexListPtr->PciePortList = PortList;
+ PcieComplexListPtr->DdiLinkList = DdiList;
+
+ InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
+}
diff --git a/src/mainboard/lenovo/g505s/PlatformGnbPcieComplex.h b/src/mainboard/lenovo/g505s/PlatformGnbPcieComplex.h
new file mode 100644
index 0000000..add9008
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/PlatformGnbPcieComplex.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
+#define _PLATFORM_GNB_PCIE_COMPLEX_H
+
+#include <vendorcode/amd/agesa/f15tn/AGESA.h>
+#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h>
+
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ );
+
+#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/lenovo/g505s/acpi/AmdImc.asl b/src/mainboard/lenovo/g505s/acpi/AmdImc.asl
new file mode 100644
index 0000000..f55a12a
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/acpi/AmdImc.asl
@@ -0,0 +1,97 @@
+//BTDC Due to IMC Fan, ACPI control codes
+OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
+Field(IMIO , ByteAcc, NoLock, Preserve) {
+ IMCX,8,
+ IMCA,8
+}
+
+IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
+ Offset(0x80),
+ MSTI, 8,
+ MITS, 8,
+ MRG0, 8,
+ MRG1, 8,
+ MRG2, 8,
+ MRG3, 8,
+}
+
+Method(WACK, 0)
+{
+ Store(0, Local0)
+ Store(50, Local1)
+ While (LAnd (LNotEqual(Local0, 0xFA), LGreater(Local1,0))) {
+ Store(MRG0, Local0)
+ Sleep(10)
+ Decrement(Local1)
+ }
+}
+
+//Init
+Method (ITZE, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
+
+//Sleep
+Method (IMSP, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(1, MRG1)
+ Store(0, MRG2)
+ Store(0x98, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0xB4, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+}
+
+//Wake
+Method (IMWK, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
diff --git a/src/mainboard/lenovo/g505s/acpi/ec.asl b/src/mainboard/lenovo/g505s/acpi/ec.asl
new file mode 100644
index 0000000..0293a12
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/acpi/ec.asl
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+/* Defines EC bits specific to the mainboard, needed by EC ASL */
+#include "mainboard.h"
+
+/* ACPI code for EC functions */
+#include <ec/compal/ene932/acpi/ec.asl>
diff --git a/src/mainboard/lenovo/g505s/acpi/gpe.asl b/src/mainboard/lenovo/g505s/acpi/gpe.asl
new file mode 100644
index 0000000..3bf0721
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/acpi/gpe.asl
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ Store("USB PME", Debug)
+ /* Notify devices of wake event */
+ Notify(\_SB.PCI0.UOH1, 0x02)
+ Notify(\_SB.PCI0.UOH2, 0x02)
+ Notify(\_SB.PCI0.UOH3, 0x02)
+ Notify(\_SB.PCI0.UOH4, 0x02)
+ Notify(\_SB.PCI0.XHC0, 0x02)
+ Notify(\_SB.PCI0.UEH1, 0x02)
+ Notify(\_SB.PWRB, 0x02)
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* Lid switch opened or closed */
+ Method(_L16) {
+ Store("Lid status changed", Debug)
+ /* Flip trigger polarity */
+ Not(LPOL, LPOL)
+ /* Notify lid object of status change */
+ Notify(\_SB.LID, 0x80)
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ Store("PCI bridge wake event", Debug)
+ /* Notify PCI bridges of wake event */
+ Notify(\_SB.PCI0.PBR4, 0x02)
+ Notify(\_SB.PCI0.PBR5, 0x02)
+ }
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+} /* End Scope GPE */
diff --git a/src/mainboard/lenovo/g505s/acpi/mainboard.asl b/src/mainboard/lenovo/g505s/acpi/mainboard.asl
new file mode 100644
index 0000000..2e87c2c
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/acpi/mainboard.asl
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+ /* Some global data */
+ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
+
+ /* Variables used by EC */
+ /* TODO: These may belong in global non-volatile storage */
+ Name(PWRS, Zero)
+
+ /* AcpiGpe0Blk */
+ OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
+ Field(GP0B, ByteAcc, NoLock, Preserve) {
+ , 11,
+ USBS, 1,
+ }
+
+ /* GPIO control block -- hardcoded to 0xfed80100 by AGESA */
+ OperationRegion (GPIO, SystemMemory, 0xfed80100, 0x100)
+ Field (GPIO, ByteAcc, NoLock, Preserve) {
+ Offset (0x39),
+ , 6,
+ GP57, 1, /* out: WLAN control (rf-kill) */
+ Offset (0x76),
+ , 7,
+ GE22, 1, /* General event 22 - connected to lid switch */
+ }
+
+ /* SMI/SCI control block -- hardcoded to 0xfed80200 by AGESA */
+ OperationRegion (SMIX, SystemMemory, 0xfed80200, 0x100)
+ Field (SMIX, AnyAcc, NoLock, Preserve) {
+ Offset (0x08), /* SCI level: 0 = active low, 1 = active high */
+ , 22,
+ LPOL, 1, /* SCI22 trigger polarity - lid switch */
+ }
+
+ /*
+ * Used by EC code on certain events
+ *
+ * From ec/compal/ene932/acpi/ec.asl:
+ * The mainboard must define a PNOT method to handle power state
+ * notifications and Notify CPU device objects to re-evaluate their
+ * _PPC and _CST tables.
+ */
+ Method (PNOT)
+ {
+ Store("Received PNOT call (probably from EC)", Debug)
+ /* TODO: Implement this */
+ }
+
+Scope (\_SB) {
+ Device (LID)
+ {
+ Name(_HID, EisaId("PNP0C0D"))
+ Name(_PRW, Package () {EC_LID_GPE, 0x04}) /* wake from S1-S4 */
+ Method(_LID, 0)
+ {
+ Return (GE22) /* GE pin 22 */
+ }
+
+ Method (_INI, 0)
+ {
+ /* Make sure lid trigger polarity is set so that we
+ * trigger an SCI when lid status changes.
+ */
+ Not(GE22, LPOL)
+ }
+ }
+
+ Device(PWRB) {
+ Name(_HID, EisaId("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_STA, 0x0B)
+ }
+
+ Device (MB) {
+ /* Lid open */
+ Method (LIDO) { /* Stub */ }
+ /* Lid closed */
+ Method (LIDC) { /* Stub */ }
+ /* Increase brightness */
+ Method (BRTU) { /* Stub */ }
+ /* Decrease brightness */
+ Method (BRTD) { /* Stub */ }
+ /* Switch display */
+ Method (DSPS) { /* Stub */ }
+ /* Toggle wireless */
+ Method (WLTG)
+ {
+ Store( Not(GP57), GP57 )
+ }
+ /* Return lid state */
+ Method (LIDS)
+ {
+ Return(GE22)
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl
new file mode 100644
index 0000000..108e204
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/acpi/routing.asl
@@ -0,0 +1,324 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+ /* Routing is in System Bus scope */
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+ Package(){0x0003FFFF, 0, INTD, 0 },
+ Package(){0x0003FFFF, 1, INTA, 0 },
+ Package(){0x0003FFFF, 2, INTB, 0 },
+ Package(){0x0003FFFF, 3, INTC, 0 },
+
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package(){0x0004FFFF, 0, INTA, 0 },
+ Package(){0x0004FFFF, 1, INTB, 0 },
+ Package(){0x0004FFFF, 2, INTC, 0 },
+ Package(){0x0004FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ Package(){0x0005FFFF, 0, INTB, 0 },
+ Package(){0x0005FFFF, 1, INTC, 0 },
+ Package(){0x0005FFFF, 2, INTD, 0 },
+ Package(){0x0005FFFF, 3, INTA, 0 },
+
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ Package(){0x0006FFFF, 0, INTC, 0 },
+ Package(){0x0006FFFF, 1, INTD, 0 },
+ Package(){0x0006FFFF, 2, INTA, 0 },
+ Package(){0x0006FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ Package(){0x0007FFFF, 0, INTD, 0 },
+ Package(){0x0007FFFF, 1, INTA, 0 },
+ Package(){0x0007FFFF, 2, INTB, 0 },
+ Package(){0x0007FFFF, 3, INTC, 0 },
+
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* SB devices */
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+ /* Bus 0, Dev 21 Pcie Bridge */
+ Package(){0x0015FFFF, 0, INTA, 0 },
+ Package(){0x0015FFFF, 1, INTB, 0 },
+ Package(){0x0015FFFF, 2, INTC, 0 },
+ Package(){0x0015FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 17 },
+ Package(){0x0001FFFF, 1, 0, 18 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+ Package(){0x0002FFFF, 0, 0, 18 },
+ Package(){0x0002FFFF, 1, 0, 19 },
+ Package(){0x0002FFFF, 2, 0, 16 },
+ Package(){0x0002FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+ Package(){0x0003FFFF, 0, 0, 19 },
+ Package(){0x0003FFFF, 1, 0, 16 },
+ Package(){0x0003FFFF, 2, 0, 17 },
+ Package(){0x0003FFFF, 3, 0, 18 },
+
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package(){0x0004FFFF, 0, 0, 16 },
+ Package(){0x0004FFFF, 1, 0, 17 },
+ Package(){0x0004FFFF, 2, 0, 18 },
+ Package(){0x0004FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ Package(){0x0005FFFF, 0, 0, 17 },
+ Package(){0x0005FFFF, 1, 0, 18 },
+ Package(){0x0005FFFF, 2, 0, 19 },
+ Package(){0x0005FFFF, 3, 0, 16 },
+
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ Package(){0x0006FFFF, 0, 0, 18 },
+ Package(){0x0006FFFF, 1, 0, 19 },
+ Package(){0x0006FFFF, 2, 0, 16 },
+ Package(){0x0006FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ Package(){0x0007FFFF, 0, 0, 19 },
+ Package(){0x0007FFFF, 1, 0, 16 },
+ Package(){0x0007FFFF, 2, 0, 17 },
+ Package(){0x0007FFFF, 3, 0, 18 },
+
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+ /* Bus0, Dev 21 PCIE Bridge */
+ Package(){0x0015FFFF, 0, 0, 16 },
+ Package(){0x0015FFFF, 1, 0, 17 },
+ Package(){0x0015FFFF, 2, 0, 18 },
+ Package(){0x0015FFFF, 3, 0, 19 },
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS7, Package(){
+ /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PE0, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 0*/
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APE0, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 0*/
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PE1, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 1*/
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APE1, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 1*/
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PE2, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 2*/
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APE2, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 2*/
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PE3, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 3 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APE3, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 3*/
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ /* SB PCI Bridge J21, J22 */
+ Name(PCIB, Package(){
+ /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+ Package(){0x0005FFFF, 0, 0, 0x14 },
+ Package(){0x0005FFFF, 1, 0, 0x15 },
+ Package(){0x0005FFFF, 2, 0, 0x16 },
+ Package(){0x0005FFFF, 3, 0, 0x17 },
+
+ Package(){0x0006FFFF, 0, 0, 0x15 },
+ Package(){0x0006FFFF, 1, 0, 0x16 },
+ Package(){0x0006FFFF, 2, 0, 0x17 },
+ Package(){0x0006FFFF, 3, 0, 0x14 },
+ })
diff --git a/src/mainboard/lenovo/g505s/acpi/sata.asl b/src/mainboard/lenovo/g505s/acpi/sata.asl
new file mode 100644
index 0000000..5ad3e47
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/acpi/sata.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* No SATA functionality */
diff --git a/src/mainboard/lenovo/g505s/acpi/si.asl b/src/mainboard/lenovo/g505s/acpi/si.asl
new file mode 100644
index 0000000..554b59d
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/acpi/si.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
diff --git a/src/mainboard/lenovo/g505s/acpi/sleep.asl b/src/mainboard/lenovo/g505s/acpi/sleep.asl
new file mode 100644
index 0000000..09b14bd
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/acpi/sleep.asl
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+
+ Store (0x07, UPWS)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* Re-enable HPET */
+ Store(1,USBS)
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/lenovo/g505s/acpi/superio.asl b/src/mainboard/lenovo/g505s/acpi/superio.asl
new file mode 100644
index 0000000..ec72e36
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/acpi/superio.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* No Super I/O device or functionality yet */
diff --git a/src/mainboard/lenovo/g505s/acpi/thermal.asl b/src/mainboard/lenovo/g505s/acpi/thermal.asl
new file mode 100644
index 0000000..0466a1b
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/acpi/thermal.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* No thermal zone functionality */
diff --git a/src/mainboard/lenovo/g505s/acpi/usb_oc.asl b/src/mainboard/lenovo/g505s/acpi/usb_oc.asl
new file mode 100644
index 0000000..1e63d97
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/acpi/usb_oc.asl
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
diff --git a/src/mainboard/lenovo/g505s/acpi_tables.c b/src/mainboard/lenovo/g505s/acpi_tables.c
new file mode 100644
index 0000000..dbe550c
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/acpi_tables.c
@@ -0,0 +1,280 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <cpu/amd/amdfam15.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+
+extern const unsigned char AmlCode[];
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ /* Just a dummy */
+ return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write Hudson IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
+
+unsigned long acpi_fill_hest(acpi_hest_t *hest)
+{
+ void *addr, *current;
+
+ /* Skip the HEST header. */
+ current = (void *)(hest + 1);
+
+ addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
+ if (addr != NULL)
+ current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+
+ addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
+ if (addr != NULL)
+ current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+
+ return (unsigned long)current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ /* Not implemented */
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+ int lens;
+ msr_t msr;
+ char pscope[] = "\\_SB.PCI0";
+
+ lens = acpigen_write_scope(pscope);
+ msr = rdmsr(TOP_MEM);
+ lens += acpigen_write_name_dword("TOM1", msr.lo);
+ msr = rdmsr(TOP_MEM2);
+ /*
+ * Since XP only implements parts of ACPI 2.0, we can't use a qword
+ * here.
+ * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+ * slide 22ff.
+ * Shift value right by 20 bit to make it fit into 32bit,
+ * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+ */
+ lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+ acpigen_patch_len(lens - 1);
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_srat_t *srat;
+ acpi_slit_t *slit;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+ acpi_header_t *ssdt;
+ acpi_header_t *alib;
+ acpi_header_t *ivrs;
+ acpi_hest_t *hest;
+
+ /* Align ACPI tables to 16 bytes */
+ start = ALIGN(start, 16);
+ current = start;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* clear all table memory */
+ memset((void *)start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /* DSDT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
+ dsdt = (acpi_header_t *)current; /* it will used by fadt */
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+ /* FACS */ /* it needs 64 bit alignment */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+ facs = (acpi_facs_t *) current; /* it will be used by fadt */
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ /* FADT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ acpi_add_table(rsdp, madt);
+
+ /* HEST */
+ current = ALIGN(current, 8);
+ hest = (acpi_hest_t *)current;
+ acpi_write_hest((void *)current);
+ acpi_add_table(rsdp, (void *)current);
+ current += ((acpi_header_t *)current)->length;
+
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
+ ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
+ if (ivrs != NULL) {
+ memcpy((void *)current, ivrs, ivrs->length);
+ ivrs = (acpi_header_t *) current;
+ current += ivrs->length;
+ acpi_add_table(rsdp, ivrs);
+ } else {
+ printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n");
+ }
+
+ /* SRAT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
+ srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+ if (srat != NULL) {
+ memcpy((void *)current, srat, srat->header.length);
+ srat = (acpi_srat_t *) current;
+ current += srat->header.length;
+ acpi_add_table(rsdp, srat);
+ } else {
+ printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n");
+ }
+
+ /* SLIT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
+ slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+ if (slit != NULL) {
+ memcpy((void *)current, slit, slit->header.length);
+ slit = (acpi_slit_t *) current;
+ current += slit->header.length;
+ acpi_add_table(rsdp, slit);
+ } else {
+ printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n");
+ }
+
+ /* ALIB */
+ current = ALIGN(current, 16);
+ printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
+ alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+ if (alib != NULL) {
+ memcpy((void *)current, alib, alib->length);
+ alib = (acpi_header_t *) current;
+ current += alib->length;
+ acpi_add_table(rsdp, (void *)alib);
+ }
+ else {
+ printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
+ }
+
+ /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */
+ /* SSDT */
+ current = ALIGN(current, 16);
+ printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
+ ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+ if (ssdt != NULL) {
+ memcpy((void *)current, ssdt, ssdt->length);
+ ssdt = (acpi_header_t *) current;
+ current += ssdt->length;
+ }
+ else {
+ printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n");
+ }
+ acpi_add_table(rsdp,ssdt);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+
+ acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/lenovo/g505s/agesawrapper.c b/src/mainboard/lenovo/g505s/agesawrapper.c
new file mode 100644
index 0000000..4cbaeaa
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/agesawrapper.c
@@ -0,0 +1,641 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "agesawrapper.h"
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include "PlatformGnbPcieComplex.h"
+
+#define __SIMPLE_DEVICE__
+
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <device/device.h>
+#include <string.h>
+#include <stdint.h>
+
+#include <cpu/amd/agesa/s3_resume.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
+
+
+#define FILECODE UNASSIGNED_FILE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* ACPI table pointers returned by AmdInitLate */
+VOID *DmiTable = NULL;
+VOID *AcpiPstate = NULL;
+VOID *AcpiSrat = NULL;
+VOID *AcpiSlit = NULL;
+
+VOID *AcpiWheaMce = NULL;
+VOID *AcpiWheaCmc = NULL;
+VOID *AcpiAlib = NULL;
+VOID *AcpiIvrs = NULL;
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+uint32_t agesawrapper_amdinitcpuio(void)
+{
+ pci_devfn_t dev;
+ msr_t msr;
+ uint32_t reg32;
+
+ dev = PCI_DEV(0, 0x18, 1);
+
+ /* Enable legacy video routing: D18F1xF4 VGA Enable */
+ pci_io_write_config32(dev, 0xf4, 1);
+
+ /* The platform BIOS needs to ensure the memory ranges of Hudson legacy
+ * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+ * set to non-posted regions.
+ * Last address before processor local APIC at FEE00000
+ */
+ pci_io_write_config32(dev, 0x84, 0x00fedf00 | (1 << 7));
+
+
+ /* Lowest NP address is HPET at FED00000 */
+ pci_io_write_config32(dev, 0x80, (0xfed00000 >> 8) | 3);
+
+ /* Map the remaining PCI hole as posted MMIO */
+ pci_io_write_config32(dev, 0x8C, 0x00fecf00);
+
+ msr = rdmsr(0xc001001a);
+ reg32 = (msr.hi << 24) | (msr.lo >> 8) | 3; /* Equivalent to msr >> 8 */
+ pci_io_write_config32(dev, 0x88, reg32);
+
+ /* Send all IO (0000-FFFF) to southbridge. */
+ pci_io_write_config32(dev, 0xc4, 0x0000f000);
+ pci_io_write_config32(dev, 0xc0, 0x00000003);
+
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS agesawrapper_amdinitmmio(void)
+{
+ AGESA_STATUS Status;
+ UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /*
+ Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+ Address MSR register.
+ */
+ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
+ LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+ /*
+ Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+ */
+ LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+ MsrReg = MsrReg | 0x0000400000000000;
+ LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+ /* For serial port */
+ PciData = 0xFF03FFD5;
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Set ROM cache onto WP to decrease post time */
+ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
+ LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
+ LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+
+ Status = AGESA_SUCCESS;
+ return Status;
+}
+
+AGESA_STATUS agesawrapper_amdinitreset(void)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_RESET_PARAMS AmdResetParams;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ LibAmdMemFill (&AmdResetParams,
+ 0,
+ sizeof (AMD_RESET_PARAMS),
+ &(AmdResetParams.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+ AmdParamStruct.AllocationMethod = ByHost;
+ AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+ AmdParamStruct.NewStructPtr = &AmdResetParams;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+ AmdResetParams.HtConfig.Depth = 0;
+
+ status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+ return status;
+}
+
+AGESA_STATUS agesawrapper_amdinitearly(void)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+
+ AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+ OemCustomizeInitEarly (AmdEarlyParamsPtr);
+
+ status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return status;
+}
+
+AGESA_STATUS agesawrapper_amdinitpost(void)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_POST_PARAMS *PostParams;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct (&AmdParamStruct);
+ PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
+ status = AmdInitPost (PostParams);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+ /* Initialize heap space */
+ EmptyHeap();
+
+ return status;
+}
+
+AGESA_STATUS agesawrapper_amdinitenv(void)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_ENV_PARAMS *EnvParam;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ status = AmdCreateStruct (&AmdParamStruct);
+ EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
+
+ status = AmdInitEnv (EnvParam);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus);
+ /* Initialize Subordinate Bus Number and Secondary Bus Number
+ * In platform BIOS this address is allocated by PCI enumeration code
+ Modify D1F0x18
+ */
+
+ return status;
+}
+
+VOID *
+agesawrapper_getlateinitptr (
+ int pick
+ )
+{
+ switch (pick) {
+ case PICK_DMI:
+ return DmiTable;
+ case PICK_PSTATE:
+ return AcpiPstate;
+ case PICK_SRAT:
+ return AcpiSrat;
+ case PICK_SLIT:
+ return AcpiSlit;
+ case PICK_WHEA_MCE:
+ return AcpiWheaMce;
+ case PICK_WHEA_CMC:
+ return AcpiWheaCmc;
+ case PICK_ALIB:
+ return AcpiAlib;
+ case PICK_IVRS:
+ return AcpiIvrs;
+ default:
+ return NULL;
+ }
+}
+
+AGESA_STATUS agesawrapper_amdinitmid(void)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+
+ /* Enable MMIO on AMD CPU Address Map Controller */
+ agesawrapper_amdinitcpuio ();
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct (&AmdParamStruct);
+
+ ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return status;
+}
+
+AGESA_STATUS agesawrapper_amdinitlate(void)
+{
+ AGESA_STATUS Status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_LATE_PARAMS *AmdLateParams;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
+ AmdCreateStruct(&AmdParamStruct);
+ AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
+ Status = AmdInitLate(AmdLateParams);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus);
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ DmiTable = AmdLateParams->DmiTable;
+ AcpiPstate = AmdLateParams->AcpiPState;
+ AcpiSrat = AmdLateParams->AcpiSrat;
+ AcpiSlit = AmdLateParams->AcpiSlit;
+
+ AcpiWheaMce = AmdLateParams->AcpiWheaMce;
+ AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
+ AcpiAlib = AmdLateParams->AcpiAlib;
+ AcpiIvrs = AmdLateParams->AcpiIvrs;
+
+ printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x,"
+ "AcpiSlit:%x, Mce:%x, Cmc:%x,"
+ "Alib:%x, AcpiIvrs:%x in %s\n",
+ (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat,
+ (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc,
+ (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
+
+ /* AmdReleaseStruct (&AmdParamStruct); */
+ return Status;
+}
+
+AGESA_STATUS agesawrapper_amdlaterunaptask (
+ UINT32 Func,
+ UINT32 Data,
+ VOID *ConfigPtr
+ )
+{
+ AGESA_STATUS Status;
+ AP_EXE_PARAMS ApExeParams;
+
+ LibAmdMemFill (&ApExeParams,
+ 0,
+ sizeof (AP_EXE_PARAMS),
+ &(ApExeParams.StdHeader));
+
+ ApExeParams.StdHeader.AltImageBasePtr = 0;
+ ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ ApExeParams.StdHeader.Func = 0;
+ ApExeParams.StdHeader.ImageBasePtr = 0;
+ ApExeParams.FunctionNumber = Func;
+ ApExeParams.RelatedDataBlock = ConfigPtr;
+
+ Status = AmdLateRunApTask (&ApExeParams);
+ if (Status != AGESA_SUCCESS) {
+ /* agesawrapper_amdreadeventlog(); */
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ return Status;
+}
+
+
+AGESA_STATUS agesawrapper_amdinitresume(void)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_RESUME_PARAMS *AmdResumeParamsPtr;
+ S3_DATA_TYPE S3DataType;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+
+ AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
+
+ AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
+ AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
+ S3DataType = S3DataTypeNonVolatile;
+ OemAgesaGetS3Info (S3DataType,
+ (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
+ (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
+
+ status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
+
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return status;
+}
+
+#ifndef __PRE_RAM__
+AGESA_STATUS agesawrapper_fchs3earlyrestore(void)
+{
+ AGESA_STATUS status = AGESA_SUCCESS;
+
+ FCH_DATA_BLOCK FchParams;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+ StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
+ StdHeader.AltImageBasePtr = 0;
+ StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ StdHeader.Func = 0;
+ StdHeader.ImageBasePtr = 0;
+
+ //FchParams = InitEnvCfgDefault;
+ FchParams.StdHeader = &StdHeader;
+ s3_resume_init_data(&FchParams);
+
+ FchInitS3EarlyRestore(&FchParams);
+
+ return status;
+}
+#endif
+
+AGESA_STATUS agesawrapper_amds3laterestore(void)
+{
+ AGESA_STATUS Status;
+ AMD_INTERFACE_PARAMS AmdInterfaceParams;
+ AMD_S3LATE_PARAMS AmdS3LateParams;
+ AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
+ S3_DATA_TYPE S3DataType;
+
+ agesawrapper_amdinitcpuio();
+ LibAmdMemFill (&AmdS3LateParams,
+ 0,
+ sizeof (AMD_S3LATE_PARAMS),
+ &(AmdS3LateParams.StdHeader));
+ AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
+ AmdInterfaceParams.AllocationMethod = ByHost;
+ AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
+ AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
+ AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdS3LateParamsPtr = &AmdS3LateParams;
+ AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
+
+ AmdCreateStruct (&AmdInterfaceParams);
+
+ AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
+ S3DataType = S3DataTypeVolatile;
+
+ OemAgesaGetS3Info (S3DataType,
+ (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
+ (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
+
+ Status = AmdS3LateRestore (AmdS3LateParamsPtr);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus);
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ return Status;
+}
+
+#ifndef __PRE_RAM__
+
+extern UINT8 picr_data[0x54], intr_data[0x54];
+
+AGESA_STATUS agesawrapper_fchs3laterestore(void)
+{
+ AGESA_STATUS status = AGESA_SUCCESS;
+
+ FCH_DATA_BLOCK FchParams;
+ AMD_CONFIG_PARAMS StdHeader;
+ UINT8 byte;
+
+ StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+ StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
+ StdHeader.AltImageBasePtr = 0;
+ StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ StdHeader.Func = 0;
+ StdHeader.ImageBasePtr = 0;
+
+ //FchParams = InitEnvCfgDefault;
+ FchParams.StdHeader = &StdHeader;
+ s3_resume_init_data(&FchParams);
+ FchInitS3LateRestore(&FchParams);
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+
+ return status;
+}
+#endif
+
+#ifndef __PRE_RAM__
+
+AGESA_STATUS agesawrapper_amdS3Save(void)
+{
+ AGESA_STATUS Status;
+ AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
+ AMD_INTERFACE_PARAMS AmdInterfaceParams;
+ S3_DATA_TYPE S3DataType;
+
+ LibAmdMemFill (&AmdInterfaceParams,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdInterfaceParams.StdHeader));
+
+ AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
+ AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+ AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdInterfaceParams.AllocationMethod = PostMemDram;
+ AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
+ AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
+ AmdInterfaceParams.StdHeader.Func = 0;
+
+ AmdCreateStruct(&AmdInterfaceParams);
+ AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
+ AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
+
+ Status = AmdS3Save(AmdS3SaveParamsPtr);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus);
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ S3DataType = S3DataTypeNonVolatile;
+ printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n",
+ (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
+ (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
+
+ Status = OemAgesaSaveS3Info (
+ S3DataType,
+ AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
+ AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
+
+ printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n",
+ (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
+ (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
+
+ if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
+ S3DataType = S3DataTypeVolatile;
+
+ Status = OemAgesaSaveS3Info (
+ S3DataType,
+ AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
+ AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
+ }
+ OemAgesaSaveMtrr();
+
+ AmdReleaseStruct (&AmdInterfaceParams);
+
+ return Status;
+}
+
+#endif /* #ifndef __PRE_RAM__ */
+
+AGESA_STATUS agesawrapper_amdreadeventlog (
+ UINT8 HeapStatus
+ )
+{
+ AGESA_STATUS Status;
+ EVENT_PARAMS AmdEventParams;
+
+ LibAmdMemFill (&AmdEventParams,
+ 0,
+ sizeof (EVENT_PARAMS),
+ &(AmdEventParams.StdHeader));
+
+ AmdEventParams.StdHeader.AltImageBasePtr = 0;
+ AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdEventParams.StdHeader.Func = 0;
+ AmdEventParams.StdHeader.ImageBasePtr = 0;
+ AmdEventParams.StdHeader.HeapStatus = HeapStatus;
+ Status = AmdReadEventLog (&AmdEventParams);
+ while (AmdEventParams.EventClass != 0) {
+ printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo);
+ printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
+ printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
+ Status = AmdReadEventLog (&AmdEventParams);
+ }
+
+ return Status;
+}
diff --git a/src/mainboard/lenovo/g505s/agesawrapper.h b/src/mainboard/lenovo/g505s/agesawrapper.h
new file mode 100644
index 0000000..29c0ee8
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/agesawrapper.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _AGESAWRAPPER_H_
+#define _AGESAWRAPPER_H_
+
+#include <stdint.h>
+#include <vendorcode/amd/agesa/f15tn/AGESA.h>
+
+/* Define AMD Ontario APPU SSID/SVID */
+#define AMD_APU_SVID 0x1022
+#define AMD_APU_SSID 0x1234
+#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
+
+enum {
+ PICK_DMI, /* DMI Interface */
+ PICK_PSTATE, /* Acpi Pstate SSDT Table */
+ PICK_SRAT, /* SRAT Table */
+ PICK_SLIT, /* SLIT Table */
+ PICK_WHEA_MCE, /* WHEA MCE table */
+ PICK_WHEA_CMC, /* WHEA CMV table */
+ PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
+ PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */
+};
+
+AGESA_STATUS agesawrapper_amdinitreset(void);
+AGESA_STATUS agesawrapper_amdinitearly(void);
+AGESA_STATUS agesawrapper_amdinitenv(void);
+AGESA_STATUS agesawrapper_amdinitlate(void);
+AGESA_STATUS agesawrapper_amdinitpost(void);
+AGESA_STATUS agesawrapper_amdinitmid(void);
+AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus);
+AGESA_STATUS agesawrapper_amdinitmmio(void);
+uint32_t agesawrapper_amdinitcpuio(void);
+void *agesawrapper_getlateinitptr (int pick);
+AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr);
+AGESA_STATUS agesawrapper_amdS3Save(void);
+AGESA_STATUS agesawrapper_amdinitresume(void);
+AGESA_STATUS agesawrapper_amds3laterestore(void);
+
+AGESA_STATUS agesawrapper_fchs3earlyrestore(void);
+AGESA_STATUS agesawrapper_fchs3laterestore(void);
+
+#endif
diff --git a/src/mainboard/lenovo/g505s/board_info.txt b/src/mainboard/lenovo/g505s/board_info.txt
new file mode 100644
index 0000000..71137bd
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/board_info.txt
@@ -0,0 +1,5 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
new file mode 100644
index 0000000..56de36e
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/buildOpts.c
@@ -0,0 +1,442 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Brazos platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
+ */
+
+#include "mainboard.h"
+
+#include <stdlib.h>
+
+#include <vendorcode/amd/agesa/f15tn/AGESA.h>
+
+/* Include the files that instantiate the configuration definitions. */
+#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
+#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
+/* AGESA nonesense: the next two headers depend on heapManager.h */
+#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
+/* These tables are optional and may be used to adjust memory timing settings */
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
+
+#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
+
+/* Select the cpu family. */
+#define INSTALL_FAMILY_10_SUPPORT FALSE
+#define INSTALL_FAMILY_12_SUPPORT FALSE
+#define INSTALL_FAMILY_14_SUPPORT FALSE
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
+
+/* Select the cpu socket type. */
+#define INSTALL_G34_SOCKET_SUPPORT FALSE
+#define INSTALL_C32_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT TRUE
+#define INSTALL_FM1_SOCKET_SUPPORT FALSE
+#define INSTALL_FP2_SOCKET_SUPPORT TRUE
+#define INSTALL_FT1_SOCKET_SUPPORT FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT FALSE
+
+#define INSTALL_FM2_SOCKET_SUPPORT FALSE
+
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
+#define BLDOPT_REMOVE_SRAT FALSE //TRUE
+#define BLDOPT_REMOVE_SLIT FALSE //TRUE
+#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_CRAT TRUE
+#define BLDOPT_REMOVE_DMI TRUE
+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
+
+//This element selects whether P-States should be forced to be independent,
+// as reported by the ACPI _PSD object. For single-link processors,
+// setting TRUE for OS to support this feature.
+
+//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT 90000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE 0
+
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_POWER_DOWN TRUE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_ONLINE_SPARE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE TRUE
+#define BLDCFG_ECC_REDIRECTION FALSE
+#define BLDCFG_SCRUB_DRAM_RATE 0
+#define BLDCFG_SCRUB_L2_RATE 0
+#define BLDCFG_SCRUB_L3_RATE 0
+#define BLDCFG_SCRUB_IC_RATE 0
+#define BLDCFG_SCRUB_DC_RATE 0
+#define BLDCFG_ECC_SYMBOL_SIZE 4
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
+#define BLDCFG_ECC_SYNC_FLOOD FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_1GB_ALIGN FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
+
+#define BLDOPT_REMOVE_ALIB FALSE
+#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled
+#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
+#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
+
+#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
+#define BLDCFG_CFG_ABM_SUPPORT 0
+
+//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
+
+// Specify the default values for the VRM controlling the VDDNB plane.
+// If not specified, the values used for the core VRM will be applied
+//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
+//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
+//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
+
+#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
+
+#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
+#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
+
+#if CONFIG_GFXUMA
+#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
+//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
+#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
+#endif
+
+#define BLDCFG_IOMMU_SUPPORT FALSE
+
+#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
+//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
+//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
+//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
+
+/* Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+#define AGESA_ENTRY_INIT_RESET TRUE
+#define AGESA_ENTRY_INIT_RECOVERY FALSE
+#define AGESA_ENTRY_INIT_EARLY TRUE
+#define AGESA_ENTRY_INIT_POST TRUE
+#define AGESA_ENTRY_INIT_ENV TRUE
+#define AGESA_ENTRY_INIT_MID TRUE
+#define AGESA_ENTRY_INIT_LATE TRUE
+#define AGESA_ENTRY_INIT_S3SAVE TRUE
+#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
+#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
+/*
+ * Customized OEM build configurations for FCH component
+ */
+// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
+// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
+// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
+// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
+// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
+// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
+// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
+// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
+// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
+// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
+// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
+// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
+// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
+// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
+// #define BLDCFG_AZALIA_SSID 0x780D1022
+// #define BLDCFG_SMBUS_SSID 0x780B1022
+// #define BLDCFG_IDE_SSID 0x780C1022
+// #define BLDCFG_SATA_AHCI_SSID 0x78011022
+// #define BLDCFG_SATA_IDE_SSID 0x78001022
+// #define BLDCFG_SATA_RAID5_SSID 0x78031022
+// #define BLDCFG_SATA_RAID_SSID 0x78021022
+// #define BLDCFG_EHCI_SSID 0x78081022
+// #define BLDCFG_OHCI_SSID 0x78071022
+// #define BLDCFG_LPC_SSID 0x780E1022
+// #define BLDCFG_SD_SSID 0x78061022
+// #define BLDCFG_XHCI_SSID 0x78121022
+// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
+// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
+// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
+
+CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
+{
+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
+ { CPU_LIST_TERMINAL }
+};
+
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
+
+ // This is the delivery package title, "BrazosPI"
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+
+/* MEMORY_BUS_SPEED */
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define DDR2100_FREQUENCY 1050 ///< DDR 2100
+#define DDR2133_FREQUENCY 1066 ///< DDR 2133
+#define DDR2400_FREQUENCY 1200 ///< DDR 2400
+#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
+#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
+#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS 0xFED00000
+#define DFLT_SMI_CMD_PORT 0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
+#define DFLT_GEC_BASE_ADDRESS 0xFED61000
+#define DFLT_AZALIA_SSID 0x780D1022
+#define DFLT_SMBUS_SSID 0x780B1022
+#define DFLT_IDE_SSID 0x780C1022
+#define DFLT_SATA_AHCI_SSID 0x78011022
+#define DFLT_SATA_IDE_SSID 0x78001022
+#define DFLT_SATA_RAID5_SSID 0x78031022
+#define DFLT_SATA_RAID_SSID 0x78021022
+#define DFLT_EHCI_SSID 0x78081022
+#define DFLT_OHCI_SSID 0x78071022
+#define DFLT_LPC_SSID 0x780E1022
+#define DFLT_SD_SSID 0x78061022
+#define DFLT_XHCI_SSID 0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+#define DFLT_FCH_GPP_LINK_CONFIG PortA4
+#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
+//#define BLDCFG_IR_PIN_CONTROL 0x33
+
+/*
+ * The GPIO control is not well documented in AGESA, but is in the BKDG
+ *
+ * Eg. FANIN1/GPIO57 on datasheet means power-on default (Function0) is to route
+ * from this ball to hardware monitor as FAN1 tacho input. Selecting Function1
+ * routes this to the GPIO block instead. Seems ACPI GPIOs and related GEVENTs
+ * are mostly in Function1, sometimes Function2.
+ *
+ * Note that the GpioOut bit does not mean that the GPIO is an output. That bit
+ * actually controls the output value, so GpioOut means "default to set".
+ * PullUpB is an inverted logic, so setting this bit means we're actually
+ * disabling the internal pull-up. The PullDown bit is NOT inverted logic.
+ * The output driver can be disabled with the GpioOutEnB bit, which is again,
+ * inverted logic. To make the list more readable, we define a few local macros
+ * to state what we mean.
+ */
+#define OUTPUT_HIGH (GpioOut)
+#define OUTPUT_LOW (0)
+#define INPUT (GpioOutEnB)
+#define PULL_UP (0)
+#define PULL_DOWN (PullDown | PullUpB)
+#define PULL_NONE (PullUpB)
+
+GPIO_CONTROL lenovo_g505s_gpio[] = {
+ {57, Function1, OUTPUT_HIGH | PULL_NONE}, /* WLAN enable */
+ {-1}
+};
+#define BLDCFG_FCH_GPIO_CONTROL_LIST (&lenovo_g505s_gpio[0])
+
+
+/* These definitions could be moved to a common Hudson header, should we decide
+ * to provide our own, saner SCI mapping function
+ */
+#define GEVENT_PIN(gpe) ((gpe) + 0x40)
+#define SCI_MAP_OHCI_12_0 0x58
+#define SCI_MAP_OHCI_13_0 0x59
+#define SCI_MAP_XHCI_10_0 0x78
+#define SCI_MAP_PWRBTN 0x73
+
+SCI_MAP_CONTROL m6_1035dx_sci_map[] = {
+ {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE},
+ {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE},
+ {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE},
+ {SCI_MAP_OHCI_12_0, PME_GPE},
+ {SCI_MAP_OHCI_13_0, PME_GPE},
+ {SCI_MAP_XHCI_10_0, PME_GPE},
+ {SCI_MAP_PWRBTN, PME_GPE},
+};
+#define BLDCFG_FCH_SCI_MAP_LIST (&m6_1035dx_sci_map[0])
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+/* AGESA nonsense: this header depends on the definitions above */
+#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform
+ * information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...).
+ * If PlatformSpecificTable is populated, AGESA will base its settings on the
+ * data from the table. Otherwise, it will use its default conservative settings
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+
+ PSO_END
+};
+
+// Customer table
+UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] =
+{
+ NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
+};
+UINT8 SizeOfTableTN = ARRAY_SIZE(AGESA_MEM_TABLE_TN);
diff --git a/src/mainboard/lenovo/g505s/cmos.layout b/src/mainboard/lenovo/g505s/cmos.layout
new file mode 100644
index 0000000..5520564
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/cmos.layout
@@ -0,0 +1,114 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#*****************************************************************************
+
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb
new file mode 100644
index 0000000..f26259c
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/devicetree.cb
@@ -0,0 +1,94 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+chip northbridge/amd/agesa/family15rl/root_complex
+
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family15rl
+ device lapic 10 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/agesa/family15rl # CPU side of HT root complex
+
+ chip northbridge/amd/agesa/family15rl # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
+ device pci 1.1 on end # Internal Multimedia
+ device pci 2.0 off end
+ device pci 3.0 off end
+ device pci 4.0 on end # PCIE MINI0
+ device pci 5.0 on end # PCIE MINI1
+ device pci 6.0 off end #
+ device pci 7.0 off end #
+ device pci 8.0 off end # NB/SB Link P2P bridge ?
+ device pci 9.0 off end #
+ end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+
+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SMBUS
+ chip drivers/generic/generic #dimm 0
+ device i2c 50 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 1
+ device i2c 51 on end # 7-bit SPD address
+ end
+ end # SM
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x439d
+ chip ec/compal/ene932
+ # 60/64 KBC
+ device pnp ff.1 on end # dummy address
+ end
+ end
+ device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO.
+ device pci 14.5 off end # USB 2
+ device pci 14.6 off end # Gec
+ device pci 14.7 off end # SD
+ device pci 15.0 off end # PCIe 0
+ device pci 15.1 off end # PCIe 1
+ device pci 15.2 off end # PCIe 2
+ device pci 15.3 off end # PCIe 3
+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
+ register "gpp_configuration" = "4"
+ end #chip southbridge/amd/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ register "spdAddrLookup" = "
+ {
+ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+ }"
+
+ end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+ end #domain
+end #chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl
new file mode 100644
index 0000000..96038ab
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/dsdt.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "mainboard.h"
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "AMD ", /* OEMID */
+ "COREBOOT", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+
+ /* Globals for the platform */
+ #include "acpi/mainboard.asl"
+
+ /* Describe the USB Overcurrent pins */
+ #include "acpi/usb_oc.asl"
+
+ /* PCI IRQ mapping for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
+
+ /* Describe the processor tree (\_PR) */
+ #include <cpu/amd/agesa/family15rl/acpi/cpu.asl>
+
+ /* Describe the supported Sleep States for this Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
+
+ /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
+ #include "acpi/sleep.asl"
+
+ Scope(\_SB) {
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+ #include "acpi/routing.asl"
+
+ Device(PCI0) {
+ /* Describe the AMD Northbridge */
+ #include <northbridge/amd/agesa/family15rl/acpi/northbridge.asl>
+
+ /* Describe the AMD Fusion Controller Hub Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
+
+ }
+
+ /* Describe PCI INT[A-H] for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
+
+ } /* End Scope(_SB) */
+
+ Scope(\_SB.PCI0.LIBR) {
+ #include "acpi/ec.asl"
+ }
+
+ /* Describe SMBUS for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
+
+ /* Define the General Purpose Events for the platform */
+ #include "acpi/gpe.asl"
+
+ /* Define the Thermal zones and methods for the platform */
+ #include "acpi/thermal.asl"
+
+ /* Define the System Indicators for the platform */
+ #include "acpi/si.asl"
+
+}
+/* End of ASL file */
diff --git a/src/mainboard/lenovo/g505s/ec.c b/src/mainboard/lenovo/g505s/ec.c
new file mode 100644
index 0000000..61f70b7
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/ec.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#include "ec.h"
+#include <ec/compal/ene932/ec.h>
+
+/* The keyboard matrix tells the EC how the keyboard is wired internally */
+static void set_keyboard_matrix_us(void)
+{
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE5);
+}
+
+/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */
+static void enter_apm_mode(void)
+{
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE9);
+}
+
+void lenovo_g505s_ec_init(void)
+{
+ set_keyboard_matrix_us();
+
+ /*
+ * The EC has a special "blinking Caps Lock LED" mode which it normally
+ * enters when it believes the OS is not responding. It occasionally
+ * disables battery charging when in this mode, although other
+ * functionality is unaffected. Although the EC starts in APM mode by
+ * default, it only leaves the "blinking Caps Lock LED" mode after
+ * receiving the following command.
+ */
+ enter_apm_mode();
+}
diff --git a/src/mainboard/lenovo/g505s/ec.h b/src/mainboard/lenovo/g505s/ec.h
new file mode 100644
index 0000000..4162b82
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/ec.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#ifndef _MAINBOARD_LENOVO_G505S_EC_H
+#define _MAINBOARD_LENOVO_G505S_EC_H
+
+#include "mainboard.h"
+
+#ifndef __SMM__
+void lenovo_g505s_ec_init(void);
+#endif
+
+#endif /* _MAINBOARD_LENOVO_G505S_EC_H */
diff --git a/src/mainboard/lenovo/g505s/irq_tables.c b/src/mainboard/lenovo/g505s/irq_tables.c
new file mode 100644
index 0000000..42364e9
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/irq_tables.c
@@ -0,0 +1,107 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdfam15.h>
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <string.h>
+#include <stdint.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c
new file mode 100644
index 0000000..4bc3dfe
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/mainboard.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include "ec.h"
+
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+
+#include <southbridge/amd/agesa/hudson/smi.h>
+
+
+static void pavilion_cold_boot_init(void)
+{
+ /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */
+ hudson_configure_gevent_smi(EC_LID_GEVENT, SMI_MODE_SMI, SMI_LVL_LOW);
+ /* EC is not powered off during S3 sleep */
+ lenovo_g505s_ec_init();
+}
+
+static void mainboard_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH);
+ hudson_enable_smi_generation();
+
+ if (acpi_is_wakeup_s3())
+ agesawrapper_fchs3earlyrestore();
+ else
+ pavilion_cold_boot_init();
+
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/lenovo/g505s/mainboard.h b/src/mainboard/lenovo/g505s/mainboard.h
new file mode 100644
index 0000000..6131df2
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/mainboard.h
@@ -0,0 +1,25 @@
+/*
+ * "The way things are connected" and a few setup options
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#ifndef _MAINBOARD_LENOVO_G505S_MAINBOARD_H
+#define _MAINBOARD_LENOVO_G505S_MAINBOARD_H
+
+/* What is connected to GEVENT pins */
+#define EC_SCI_GEVENT 3
+#define EC_LID_GEVENT 22
+#define EC_SMI_GEVENT 23
+#define PCIE_GEVENT 8
+
+/* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but
+ * we make the distinction between GEVENT pin and SCI.
+ */
+#define EC_SCI_GPE EC_SCI_GEVENT
+#define EC_LID_GPE EC_LID_GEVENT
+#define PME_GPE 0x0b
+#define PCIE_GPE 0x18
+
+#endif /* _MAINBOARD_LENOVO_G505S_MAINBOARD_H */
diff --git a/src/mainboard/lenovo/g505s/mainboard_smi.c b/src/mainboard/lenovo/g505s/mainboard_smi.c
new file mode 100644
index 0000000..386d390
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/mainboard_smi.c
@@ -0,0 +1,107 @@
+/*
+ * SMI handler -- mostly takes care of SMIs from the EC
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+#include "ec.h"
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <delay.h>
+#include <ec/compal/ene932/ec.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <southbridge/amd/agesa/hudson/smi.h>
+
+#define ACPI_PM1_CNT_SLEEP(state) ((1 << 13) | (state & 0x7) << 10)
+
+enum sleep_states {
+ S0 = 0,
+ S1 = 1,
+ S3 = 3,
+ S4 = 4,
+ S5 = 5,
+};
+
+enum ec_smi_event {
+ EC_SMI_EVENT_IDLE = 0x80,
+ EC_SMI_BATTERY_LOW = 0xb3,
+};
+
+/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */
+static void ec_enter_apm_mode(void)
+{
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE9);
+}
+/* Tell EC to operate in ACPI mode, thus generating SCIs on events, not SMIs */
+static void ec_enter_acpi_mode(void)
+{
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE8);
+}
+
+static uint8_t ec_get_smi_event(void)
+{
+ ec_kbc_write_cmd(0x56);
+ return ec_kbc_read_ob();
+}
+
+static void ec_process_smi(uint8_t src)
+{
+ /* Reading the SMI source satisfies the EC in terms of responding to
+ * the event, regardless of whether we take an action or not.
+ */
+
+ switch (src) {
+ case EC_SMI_BATTERY_LOW:
+ printk(BIOS_DEBUG, "Battery low. Shutting down\n");
+ outl(ACPI_PM1_CNT_SLEEP(S5), ACPI_PM1_CNT_BLK);
+ break;
+ default:
+ printk(BIOS_DEBUG, "EC_SMI event 0x%x\n", src);
+ }
+}
+
+static void handle_ec_smi(void)
+{
+ uint8_t src;
+
+ while ((src = ec_get_smi_event()) != EC_SMI_EVENT_IDLE)
+ ec_process_smi(src);
+}
+
+static void handle_lid_smi(void)
+{
+ /* Only triggered in non-ACPI mode on lid close. */
+ outl(ACPI_PM1_CNT_SLEEP(S4), ACPI_PM1_CNT_BLK);
+}
+
+int mainboard_smi_apmc(uint8_t data)
+{
+ switch (data) {
+ case ACPI_SMI_CMD_ENABLE:
+ printk(BIOS_DEBUG, "Enable ACPI mode\n");
+ ec_enter_acpi_mode();
+ hudson_disable_gevent_smi(EC_LID_GEVENT);
+ break;
+ case ACPI_SMI_CMD_DISABLE:
+ printk(BIOS_DEBUG, "Disable ACPI mode\n");
+ ec_enter_apm_mode();
+ hudson_configure_gevent_smi(EC_LID_GEVENT, SMI_MODE_SMI,
+ SMI_LVL_LOW);
+ break;
+ default:
+ printk(BIOS_DEBUG, "Unhandled ACPI command: 0x%x\n", data);
+ }
+ return 0;
+}
+
+void mainboard_smi_gpi(uint32_t gpi_sts)
+{
+ if (gpi_sts & (1 << EC_SMI_GEVENT))
+ handle_ec_smi();
+ if (gpi_sts & (1 << EC_LID_GEVENT))
+ handle_lid_smi();
+}
diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c
new file mode 100644
index 0000000..f47b9d9
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/mptable.c
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/smp/mpspec.h>
+#include <console/console.h>
+#include <cpu/amd/amdfam15.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci.h>
+#include <stdint.h>
+#include <string.h>
+#include <southbridge/amd/agesa/hudson/hudson.h> /* pm_ioread() */
+
+
+u8 picr_data[0x54] = {
+ 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F
+};
+u8 intr_data[0x54] = {
+ 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x10,0x11,0x12,0x13
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ u8 byte;
+
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ memcpy(mc->mpc_oem, "AMD ", 8);
+
+ smp_write_processors(mc);
+
+ //mptable_write_buses(mc, NULL, &bus_isa);
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ bus_isa = 0x02;
+ my_smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+ /* Internal VGA */
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+ /* SMBUS */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+ /* on board NIC & Slot PCIE. */
+
+ /* PCI slots */
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
+
+ /* PCIe Lan*/
+ PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+ /* FCH PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* FCH PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* FCH PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* FCH PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c
new file mode 100644
index 0000000..01f463a
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/romstage.c
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+#include <northbridge/amd/agesa/agesawrapper_call.h>
+
+#include <arch/acpi.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/amd/car.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <stdint.h>
+#include <string.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+ AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+
+ hudson_lpc_port80();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+
+ post_code(0x31);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ post_code(0x37);
+ AGESAWRAPPER(amdinitreset);
+ post_code(0x39);
+
+ AGESAWRAPPER(amdinitearly);
+ int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ if (!s3resume) {
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ disable_cache_as_ram();
+ } else { /* S3 detect */
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ AGESAWRAPPER(amdinitresume);
+
+ AGESAWRAPPER(amds3laterestore);
+
+ post_code(0x61);
+ prepare_for_resume();
+ }
+
+ post_code(0x50);
+ copy_and_run();
+
+ post_code(0x54); /* Should never see this post code. */
+}
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