[coreboot-gerrit] Patch set updated for coreboot: 6dea028 i82801gx: Enable upper CMOS in bootblock.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Sat Nov 22 21:21:15 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7556
-gerrit
commit 6dea0282ea78e88f2334b1a9044178a0c940f0d0
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Sat Nov 22 20:36:58 2014 +0100
i82801gx: Enable upper CMOS in bootblock.
Otherwise checksum may not work correctly on early stages.
Change-Id: Ie541d71bd76af182e445aa5ef21fe5ba77091159
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/apple/macbook21/romstage.c | 3 ---
src/mainboard/getac/p470/romstage.c | 3 ---
src/mainboard/ibase/mb899/romstage.c | 3 ---
src/mainboard/intel/d945gclf/romstage.c | 3 ---
src/mainboard/kontron/986lcd-m/romstage.c | 3 ---
src/mainboard/lenovo/t60/romstage.c | 3 ---
src/mainboard/lenovo/x60/romstage.c | 3 ---
src/mainboard/roda/rk886ex/romstage.c | 3 ---
src/southbridge/intel/i82801gx/bootblock.c | 7 +++++++
9 files changed, 7 insertions(+), 24 deletions(-)
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 8d3fc67..612f614 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -215,9 +215,6 @@ static void rcba_config(void)
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index ccfb076..c416fb7 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -190,9 +190,6 @@ static void rcba_config(void)
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 2a81921..f66f51d 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -162,9 +162,6 @@ static void rcba_config(void)
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
}
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 4508968..4194a80 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -89,9 +89,6 @@ static void rcba_config(void)
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Disable unused devices */
//RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
// RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 2c89e6c..699cf12 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -221,9 +221,6 @@ static void rcba_config(void)
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Now, this is a bit ugly. As per PCI specification, function 0 of a
* device always has to be implemented. So disabling ethernet port 1
* would essentially disable all three ethernet ports of the mainboard.
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index f0ebcbc..4f7106e 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -136,9 +136,6 @@ static void rcba_config(void)
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 1310b33..d8c982b 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -143,9 +143,6 @@ static void rcba_config(void)
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 071fa2a..905d968 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -168,9 +168,6 @@ static void rcba_config(void)
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
- /* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index 7b4cd7d..d8e03b7 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -19,6 +19,7 @@
#include <arch/io.h>
#include <cpu/x86/tsc.h>
+#include "i82801gx.h"
static void store_initial_timestamp(void)
{
@@ -50,4 +51,10 @@ static void bootblock_southbridge_init(void)
store_initial_timestamp();
#endif
enable_spi_prefetch();
+
+ /* Enable RCBA */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(0x3400) = (1 << 2);
}
More information about the coreboot-gerrit
mailing list