[coreboot-gerrit] New patch to review for coreboot: 953a651 vendorcode/amd/agesa/f15?tn: Remove trivial differences between files
Damien Zammit (damien@zamaudio.com)
gerrit at coreboot.org
Tue Nov 18 13:33:01 CET 2014
Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7511
-gerrit
commit 953a65177a7734d04397275e71da989a2805a34b
Author: Damien Zammit <damien at zamaudio.com>
Date: Tue Nov 18 23:29:15 2014 +1100
vendorcode/amd/agesa/f15?tn: Remove trivial differences between files
Change-Id: I061e800d49ebc6d4aed44763892a9625613dd9d8
Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
src/vendorcode/amd/agesa/f15/AGESA.h | 62 ++--
src/vendorcode/amd/agesa/f15/Include/Filecode.h | 21 +-
src/vendorcode/amd/agesa/f15/Include/Ids.h | 3 +-
.../amd/agesa/f15/Include/OptionApmInstall.h | 1 -
.../amd/agesa/f15/Include/OptionC6Install.h | 1 -
.../amd/agesa/f15/Include/OptionCpbInstall.h | 1 -
.../f15/Include/OptionCpuCacheFlushOnHaltInstall.h | 1 -
.../f15/Include/OptionCpuCoreLevelingInstall.h | 1 -
.../agesa/f15/Include/OptionCpuFamiliesInstall.h | 1 -
.../agesa/f15/Include/OptionCpuFeaturesInstall.h | 1 -
.../amd/agesa/f15/Include/OptionDmiInstall.h | 1 -
.../amd/agesa/f15/Include/OptionFamily15hInstall.h | 1 -
.../amd/agesa/f15/Include/OptionGnbInstall.h | 7 +-
.../amd/agesa/f15/Include/OptionHtInstall.h | 1 -
.../amd/agesa/f15/Include/OptionIdsInstall.h | 1 -
.../amd/agesa/f15/Include/OptionIoCstateInstall.h | 1 -
.../agesa/f15/Include/OptionL3FeaturesInstall.h | 1 -
.../amd/agesa/f15/Include/OptionMemoryInstall.h | 302 ++++++++--------
.../f15/Include/OptionMemoryRecoveryInstall.h | 1 -
.../agesa/f15/Include/OptionMsgBasedC1eInstall.h | 1 -
.../f15/Include/OptionPreserveMailboxInstall.h | 1 -
.../agesa/f15/Include/OptionPstateHpcModeInstall.h | 1 -
.../amd/agesa/f15/Include/OptionPstateInstall.h | 1 -
src/vendorcode/amd/agesa/f15/Include/Options.h | 1 -
.../amd/agesa/f15/Include/PlatformInstall.h | 1 -
src/vendorcode/amd/agesa/f15/Legacy/agesa.inc | 95 +++--
src/vendorcode/amd/agesa/f15/Lib/amdlib.c | 8 +-
src/vendorcode/amd/agesa/f15/cpcar.inc | 8 +-
src/vendorcode/amd/agesa/f15/gcccar.inc | 5 -
src/vendorcode/amd/agesa/f15tn/AGESA.h | 397 ++++++++++-----------
src/vendorcode/amd/agesa/f15tn/Include/Filecode.h | 2 +-
.../amd/agesa/f15tn/Include/GnbInterface.h | 13 +-
src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h | 3 +-
src/vendorcode/amd/agesa/f15tn/Include/Ids.h | 14 +-
.../amd/agesa/f15tn/Include/OptionApmInstall.h | 2 +-
.../amd/agesa/f15tn/Include/OptionC6Install.h | 3 +-
.../amd/agesa/f15tn/Include/OptionCpbInstall.h | 3 +-
.../Include/OptionCpuCacheFlushOnHaltInstall.h | 3 +-
.../f15tn/Include/OptionCpuCoreLevelingInstall.h | 4 +-
.../agesa/f15tn/Include/OptionCpuFamiliesInstall.h | 5 +-
.../agesa/f15tn/Include/OptionCpuFeaturesInstall.h | 2 +-
.../amd/agesa/f15tn/Include/OptionDmiInstall.h | 2 +-
.../agesa/f15tn/Include/OptionFamily15hInstall.h | 4 +-
.../amd/agesa/f15tn/Include/OptionFchInstall.h | 49 +--
src/vendorcode/amd/agesa/f15tn/Include/OptionGnb.h | 3 +-
.../amd/agesa/f15tn/Include/OptionGnbInstall.h | 60 ++--
.../amd/agesa/f15tn/Include/OptionHtInstall.h | 4 +-
.../amd/agesa/f15tn/Include/OptionIdsInstall.h | 2 +-
.../agesa/f15tn/Include/OptionIoCstateInstall.h | 2 +-
.../agesa/f15tn/Include/OptionL3FeaturesInstall.h | 2 +-
.../amd/agesa/f15tn/Include/OptionMemory.h | 3 +-
.../amd/agesa/f15tn/Include/OptionMemoryInstall.h | 10 +-
.../f15tn/Include/OptionMemoryRecoveryInstall.h | 2 +-
.../agesa/f15tn/Include/OptionMsgBasedC1eInstall.h | 2 +-
.../amd/agesa/f15tn/Include/OptionMultiSocket.h | 3 +-
.../f15tn/Include/OptionPreserveMailboxInstall.h | 2 +-
.../f15tn/Include/OptionPstateHpcModeInstall.h | 2 +-
.../amd/agesa/f15tn/Include/OptionPstateInstall.h | 2 +-
src/vendorcode/amd/agesa/f15tn/Include/Options.h | 4 +-
src/vendorcode/amd/agesa/f15tn/Include/OptionsHt.h | 5 +-
.../amd/agesa/f15tn/Include/OptionsPage.h | 4 +-
.../amd/agesa/f15tn/Include/PlatformInstall.h | 12 +-
.../f15tn/Include/PlatformMemoryConfiguration.h | 5 +-
.../f15tn/Legacy/PlatformMemoryConfiguration.inc | 51 +--
.../amd/agesa/f15tn/Legacy/Proc/Dispatcher.c | 3 +-
.../amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c | 5 +-
.../amd/agesa/f15tn/Legacy/Proc/arch2008.asm | 49 +--
.../amd/agesa/f15tn/Legacy/Proc/hobTransfer.c | 3 +-
src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc | 49 +--
src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c | 12 +-
src/vendorcode/amd/agesa/f15tn/Lib/amdlib.h | 6 +-
.../amd/agesa/f15tn/Lib/x64/amdlib64.asm | 49 +--
src/vendorcode/amd/agesa/f15tn/cpcar.inc | 50 +--
73 files changed, 705 insertions(+), 738 deletions(-)
diff --git a/src/vendorcode/amd/agesa/f15/AGESA.h b/src/vendorcode/amd/agesa/f15/AGESA.h
index 6b0171b..e9351ea 100644
--- a/src/vendorcode/amd/agesa/f15/AGESA.h
+++ b/src/vendorcode/amd/agesa/f15/AGESA.h
@@ -38,7 +38,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
@@ -729,7 +728,6 @@ typedef enum {
// Event definitions
-
#define GNB_EVENT_INVALID_CONFIGURATION 0x20010000 // User configuration invalid
#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001 // Requested lane allocation for PCIe port can not be supported
#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION 0x20010002 // Requested incorrect PCIe port device address
@@ -2138,44 +2136,44 @@ typedef union {
#define MEM_ERROR_TRAINING_SEED_NOT_FOUND 0x040D3500 ///< No training seed is found
// AGESA_WARNING Memory Errors
-#define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600 ///< QR DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600 ///< U DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600 ///< SO-DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600 ///< x4 DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600 ///< R DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_LRDIMM 0x04061600 ///< LR DIMMs detected but not supported
-#define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700 ///< Processor is not capable for EMP
-#define MEM_WARNING_EMP_CONFLICT 0x04021700 ///< EMP cannot be enabled if channel interleaving,
-#define MEM_WARNING_EMP_NOT_ENABLED 0x04031700 ///< Memory size is not power of two.
-#define MEM_WARNING_ECC_DIS 0x04041700 ///< ECC has been disabled as a result of an internal issue
+#define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600 ///< QR DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600 ///< U DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600 ///< SO-DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600 ///< x4 DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600 ///< R DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_LRDIMM 0x04061600 ///< LR DIMMs detected but not supported
+#define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700 ///< Processor is not capable for EMP
+#define MEM_WARNING_EMP_CONFLICT 0x04021700 ///< EMP cannot be enabled if channel interleaving,
+#define MEM_WARNING_EMP_NOT_ENABLED 0x04031700 ///< Memory size is not power of two.
+#define MEM_WARNING_ECC_DIS 0x04041700 ///< ECC has been disabled as a rest of an internal issue
#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800 ///< Performance has been enabled, but battery life is preferred.
///< bank interleaving, or bank swizzle is enabled.
-#define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900 ///< No Trc timing value found in SPD of a dimm.
-#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000 ///< Node Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900 ///< No Trc timing value found in SPD of a dimm.
+#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000 ///< Node Interleaveing Requested, but could not be enabled
#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100 ///< Channel Interleaveing Requested, but could not be enabled
#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200 ///< Bank Interleaveing Requested, but could not be enabled
-#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported
-#define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO 0x04012400 ///< DDR3 voltage initial value is not 0
+#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported
+#define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO 0x04012400 ///< DDR3 voltage initial value is not 0
#define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO 0x04012500 ///< Cannot find a commonly supported VDDIO
// AGESA_FATAL Memory Errors
-#define MEM_ERROR_MINIMUM_MODE 0x04011A00 ///< Running in minimum mode
-#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00 ///< DIMM modules are miss-matched
-#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00 ///< No DIMMs have been found
-#define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00 ///< DIMM clocks miss-matched
-#define MEM_ERROR_NO_CYC_TIME 0x04011E00 ///< No cycle time found
-#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00 ///< Heap allocation error with dynamic storing of trained timings
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00 ///< Heap allocation error for SPD data
+#define MEM_ERROR_MINIMUM_MODE 0x04011A00 ///< Running in minimum mode
+#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00 ///< DIMM modules are miss-matched
+#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00 ///< No DIMMs have been found
+#define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00 ///< DIMM clocks miss-matched
+#define MEM_ERROR_NO_CYC_TIME 0x04011E00 ///< No cycle time found
+#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00 ///< Heap allocation error with dynamic storing of trained timings
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00 ///< Heap allocation error for SPD data
#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00 ///< Heap allocation error for RECEIVED_DATA during parallel training
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00 ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00 ///< Heap allocation error for Training Data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00 ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00 ///< Heap allocation error for Training Data
#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00 ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK
#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300 ///< No Constructor for DIMM Identify
-#define MEM_ERROR_VDDIO_UNSUPPORTED 0x04022500 ///< VDDIO of the dimms on the board is not supported
-#define MEM_ERROR_HEAP_ALLOCATE_FOR___ 0x040B1F00 ///< Heap allocation error for training data
-#define MEM_ERROR_HEAP_DEALLOCATE_FOR___ 0x040C1F00 ///< Heap de-allocation error for training data
+#define MEM_ERROR_VDDIO_UNSUPPORTED 0x04022500 ///< VDDIO of the dimms on the board is not supported
+#define MEM_ERROR_HEAP_ALLOCATE_FOR___ 0x040B1F00 ///< Heap allocation error for training data
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR___ 0x040C1F00 ///< Heap de-allocation error for training data
// AGESA_CRITICAL Memory Errors
#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00 ///< Heap allocation error for DMI table for DDR3
@@ -2848,7 +2846,7 @@ typedef struct _PLATFORM_CONFIGURATION {
/**********************************************************************
* Structures for: AmdInitLate
**********************************************************************/
-#define PROC_VERSION_LENGTH 48
+#define PROC_VERSION_LENGTH 48
#define MAX_DIMMS_PER_SOCKET 16
/* Interface Parameter Structures */
@@ -3255,7 +3253,7 @@ AmdInitPost (
typedef struct {
IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
- IN GNB_ENV_CONFIGURATION GnbEnvConfiguration; ///< platform operational characteristics.
+ IN GNB_ENV_CONFIGURATION GnbEnvConfiguration; ///< GNB configuration
IN FCH_INTERFACE FchInterface; ///< FCH configuration
} AMD_ENV_PARAMS;
diff --git a/src/vendorcode/amd/agesa/f15/Include/Filecode.h b/src/vendorcode/amd/agesa/f15/Include/Filecode.h
index 0d9f67a..09fc37b 100644
--- a/src/vendorcode/amd/agesa/f15/Include/Filecode.h
+++ b/src/vendorcode/amd/agesa/f15/Include/Filecode.h
@@ -41,7 +41,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _FILECODE_H_
@@ -103,16 +102,16 @@
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049)
#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE (0xA04A)
#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE (0xA04B)
-#define PROC_GNB_NB_FAMILY_LN_F12NBPOWERGATE_FILECODE (0xA04C)
-#define PROC_GNB_NB_FAMILY_LN_F12NBSERVICES_FILECODE (0xA04D)
-#define PROC_GNB_NB_FAMILY_LN_F12NBSMU_FILECODE (0xA04E)
+#define PROC_GNB_NB_FAMILY_LN_F12NBPOWERGATE_FILECODE (0xA04C)
+#define PROC_GNB_NB_FAMILY_LN_F12NBSERVICES_FILECODE (0xA04D)
+#define PROC_GNB_NB_FAMILY_LN_F12NBSMU_FILECODE (0xA04E)
#define PROC_GNB_NB_FAMILY_ON_F14NBLCLKNCLKRATIO_FILECODE (0xA04F)
#define PROC_GNB_NB_FAMILY_ON_F14NBPOWERGATE_FILECODE (0xA050)
#define PROC_GNB_NB_FAMILY_ON_F14NBSERVICES_FILECODE (0xA051)
#define PROC_GNB_NB_FAMILY_ON_F14NBSMU_FILECODE (0xA052)
#define PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE (0xA053)
#define PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE (0xA054)
-#define PROC_GNB_NB_FAMILY_LN_F12NBLCLKDPM_FILECODE (0xA055)
+#define PROC_GNB_NB_FAMILY_LN_F12NBLCLKDPM_FILECODE (0xA055)
#define PROC_GNB_NB_FAMILY_ON_F14NBLCLKDPM_FILECODE (0xA056)
#define PROC_GNB_NB_NBCONFIGDATA_FILECODE (0xA060)
#define PROC_GNB_NB_NBINIT_FILECODE (0xA061)
@@ -123,12 +122,12 @@
#define PROC_GNB_NB_NBINITATRESET_FILECODE (0xA072)
#define PROC_GNB_NB_NBPOWERMGMT_FILECODE (0xA073)
#define PROC_GNB_NB_NBSMULIB_FILECODE (0xA074)
-#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEALIB_FILECODE (0xA075)
-#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXCONFIG_FILECODE (0xA076)
-#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXSERVICES_FILECODE (0xA077)
-#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPHYSERVICES_FILECODE (0xA078)
-#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPIFSERVICES_FILECODE (0xA079)
-#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEWRAPPERSERVICES_FILECODE (0xA07A)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEALIB_FILECODE (0xA075)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXCONFIG_FILECODE (0xA076)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXSERVICES_FILECODE (0xA077)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPHYSERVICES_FILECODE (0xA078)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPIFSERVICES_FILECODE (0xA079)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEWRAPPERSERVICES_FILECODE (0xA07A)
#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEALIB_FILECODE (0xA07D)
#define PROC_GNB_PCIE_FAMILY_ON_F14PCIECOMPLEXCONFIG_FILECODE (0xA07E)
#define PROC_GNB_PCIE_FAMILY_ON_F14PCIECOMPLEXSERVICES_FILECODE (0xA07F)
diff --git a/src/vendorcode/amd/agesa/f15/Include/Ids.h b/src/vendorcode/amd/agesa/f15/Include/Ids.h
index b8d5091..9100e74 100644
--- a/src/vendorcode/amd/agesa/f15/Include/Ids.h
+++ b/src/vendorcode/amd/agesa/f15/Include/Ids.h
@@ -38,7 +38,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
/* Macros to aid debugging */
@@ -1083,7 +1082,7 @@ IdsExceptionTrap (
#define IEM_SKIP_CODE(L)
#endif
#ifndef IEM_INSERT_CODE
- #define IEM_INSERT_CODE(L,Fn,Parm)
+ #define IEM_INSERT_CODE(L, Fn, Parm)
#endif
//Note a is from 0 to 63
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionApmInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionApmInstall.h
index 4b3b9a8..d8e2d79 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionApmInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionApmInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_APM_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionC6Install.h b/src/vendorcode/amd/agesa/f15/Include/OptionC6Install.h
index 2e944bf..cd5555b 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionC6Install.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionC6Install.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_C6_STATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpbInstall.h
index d47619b..3b17ff3 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionCpbInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpbInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_CPB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpuCacheFlushOnHaltInstall.h
index 35362ff..58446dc 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionCpuCacheFlushOnHaltInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpuCacheFlushOnHaltInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpuCoreLevelingInstall.h
index d0743ec..dadd601 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionCpuCoreLevelingInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpuCoreLevelingInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpuFamiliesInstall.h
index 5cc4819..ee6cb8e 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionCpuFamiliesInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpuFamiliesInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
/* Default all CPU Specific Service members to off. They
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpuFeaturesInstall.h
index 44df5ba..b12661f 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionCpuFeaturesInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpuFeaturesInstall.h
@@ -38,7 +38,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h
index a6d48b3..0054403 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_DMI_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hInstall.h
index 73eeb6f..6f90846 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hInstall.h
@@ -38,7 +38,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_FAMILY_15H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionGnbInstall.h
index 7733859..2ded3a8 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionGnbInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionGnbInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_GNB_INSTALL_H_
@@ -148,8 +147,8 @@
#endif
#ifndef CFG_ORB_CLOCK_GATING_ENABLE
- #define CFG_ORB_CLOCK_GATING_ENABLE TRUE
- #endif
+ #define CFG_ORB_CLOCK_GATING_ENABLE TRUE
+ #endif
#ifndef CFG_GNB_PCIE_POWERGATING_FLAGS
#define CFG_GNB_PCIE_POWERGATING_FLAGS 0x0
@@ -308,7 +307,7 @@
OPTION_GNB_FEATURE GfxConfigPostInterface;
#define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface},
#else
- #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
+ #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_POST_INIT
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionHtInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionHtInstall.h
index 056777d..de54dfd 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionHtInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionHtInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_HT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h
index a2c0034..79e5764 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h
@@ -38,7 +38,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_IDS_INSTALL_H_
#define _OPTION_IDS_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionIoCstateInstall.h
index f83ad70..60cfba4 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionIoCstateInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionIoCstateInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_IO_CSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h
index 5804f1d..cd6aeea 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_L3_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h
index 24c1ae8..29f21b1 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_MEMORY_INSTALL_H_
@@ -497,7 +496,6 @@ BOOLEAN MemFS3DefConstructorRet (
#define MEM_TECH_CONSTRUCTOR_DDR3
#endif
-
/*---------------------------------------------------------------------------------------------------
* FEATURE BLOCKS
*
@@ -871,8 +869,8 @@ BOOLEAN MemFS3DefConstructorRet (
#define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
#endif
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemFDefRet
+ #undef MEM_TECH_FEATURE_CPG
+ #define MEM_TECH_FEATURE_CPG MemFDefRet
#if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
#undef MEM_TECH_FEATURE_HWRXEN
@@ -964,33 +962,33 @@ BOOLEAN MemFS3DefConstructorRet (
#define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect
#else
#define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef
- #endif
- #endif
+ #endif
+ #endif
#if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
#define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1
- #else
+ #else
#define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
+ #endif
#if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
#define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #else
+ #else
#define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
+ #endif
#if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
#define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw
- #else
+ #else
#define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
+ #endif
#if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
#define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
#else
#define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
+ #endif
#if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
#define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency
#else
#define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #endif
+ #endif
#define TECH_TRAIN_DQS____DDR2 MemTFeatDef
MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Dr = {
MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
@@ -1038,62 +1036,62 @@ BOOLEAN MemFS3DefConstructorRet (
#if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
#define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
#define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
- #else
+ #else
#define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
#define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #endif
+ #endif
#if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
#define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #else
+ #else
#define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #endif
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+ #endif
+ #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
#define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1
#define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2
#if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
#undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
#define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3
- #else
+ #else
#if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
#define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect
- #else
+ #else
#define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
- #endif
- #endif
- #else
+ #endif
+ #endif
+ #else
#define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
#define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
#if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
#define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect
- #else
+ #else
#define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+ #endif
#endif
- #endif
#if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
#define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1
#else
#define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
+ #endif
#if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
#define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1
#else
#define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
+ #endif
#if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
#define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
+ #else
#define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
+ #endif
#if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
#define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
+ #else
#define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
+ #endif
#if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
#define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
- #else
+ #else
#define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #endif
+ #endif
#define TECH_TRAIN_DQS____DDR3 MemTFeatDef
#define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
@@ -1113,7 +1111,7 @@ BOOLEAN MemFS3DefConstructorRet (
TECH_TRAIN_MAX_RD_LAT_DDR3,
TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
TECH_TRAIN_DQS____DDR3
- };
+ };
#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr },
#else
#undef TECH_TRAIN_ENTER_HW_TRN_DDR3
@@ -1133,10 +1131,10 @@ BOOLEAN MemFS3DefConstructorRet (
#define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
#endif
- #else
+ #else
#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
+ #endif
#if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB)
#if OPTION_DDR2
@@ -1330,7 +1328,7 @@ BOOLEAN MemFS3DefConstructorRet (
#undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
#define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect
#else
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+ #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
#define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect
#else
#define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
@@ -1925,7 +1923,7 @@ BOOLEAN MemFS3DefConstructorRet (
#if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
#define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
#else
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+ #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
#endif
#if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
#ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
@@ -2087,11 +2085,11 @@ BOOLEAN MemFS3DefConstructorRet (
#define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUHy3,
#else
#define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #else
+ #endif
+ #else
#define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef,
#define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef,
- #endif
+ #endif
#if OPTION_RDIMMS
#if OPTION_DDR2
#define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef,
@@ -2100,13 +2098,13 @@ BOOLEAN MemFS3DefConstructorRet (
#endif
#if OPTION_DDR3
#define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsRHy3,
- #else
+ #else
#define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef,
- #endif
+ #endif
#else
#define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef,
#define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef,
- #endif
+ #endif
#if OPTION_SODIMMS
#if OPTION_DDR2
#define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef,
@@ -2118,18 +2116,18 @@ BOOLEAN MemFS3DefConstructorRet (
#else
#define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef,
#endif
- #else
+ #else
#define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef,
#define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
+ #endif
+ #else
#define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef,
#define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef,
#define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef,
#define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef,
#define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef,
#define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef,
- #endif
+ #endif
MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
PLAT_SP_HY_FF_UDIMM2
PLAT_SP_HY_FF_RDIMM2
@@ -2160,41 +2158,41 @@ BOOLEAN MemFS3DefConstructorRet (
#if OPTION_DDR2
extern MEM_PLAT_SPEC_CFG MemPConstructPsRDr2;
#define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsRDr2,
- #else
+ #else
#define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
+ #endif
+ #if OPTION_DDR3
#define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsRDr3,
#else
#define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef,
#endif
- #else
+ #else
#define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef,
#define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef,
- #endif
+ #endif
#if OPTION_SODIMMS
#if OPTION_DDR2
#define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef,
#else
#define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef,
- #endif
+ #endif
#if OPTION_DDR3
#define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsSDr3,
#else
#define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef,
#endif
- #else
+ #else
#define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef,
#define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
+ #endif
+ #else
#define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef,
#define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef,
#define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef,
#define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef,
#define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef,
#define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef,
- #endif
+ #endif
MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = {
PLAT_SP_DR_FF_UDIMM2
PLAT_SP_DR_FF_RDIMM2
@@ -2216,10 +2214,10 @@ BOOLEAN MemFS3DefConstructorRet (
#else
#define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef,
#endif
- #else
+ #else
#define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef,
#define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef,
- #endif
+ #endif
#if OPTION_RDIMMS
#if OPTION_DDR2
#define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef,
@@ -2238,26 +2236,26 @@ BOOLEAN MemFS3DefConstructorRet (
#if OPTION_SODIMMS
#if OPTION_DDR2
#define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsSDA2,
- #else
+ #else
#define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
+ #endif
+ #if OPTION_DDR3
#define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsSDA3,
#else
#define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef,
#endif
- #else
+ #else
#define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef,
#define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
+ #endif
+ #else
#define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef,
#define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef,
#define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef,
#define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef,
#define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef,
#define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef,
- #endif
+ #endif
MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
PLAT_SP_DA_FF_UDIMM2
PLAT_SP_DA_FF_RDIMM2
@@ -2274,7 +2272,7 @@ BOOLEAN MemFS3DefConstructorRet (
#define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsSNi3,
#define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef,
#define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUNi3,
- #else
+ #else
#define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef,
#define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef,
#define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef,
@@ -2298,14 +2296,14 @@ BOOLEAN MemFS3DefConstructorRet (
#define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsSPh3,
#define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef,
#define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUPh3,
- #else
+ #else
#define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef,
#define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef,
#define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef,
#define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsUDef,
#define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef,
#define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUDef,
- #endif
+ #endif
MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
PLAT_SP_PH_FF_UDIMM2
PLAT_SP_PH_FF_RDIMM2
@@ -2329,7 +2327,7 @@ BOOLEAN MemFS3DefConstructorRet (
#define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsUDef,
#define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef,
#define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsUDef,
- #endif
+ #endif
MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
PLAT_SP_RB_FF_UDIMM2
PLAT_SP_RB_FF_RDIMM2
@@ -2351,10 +2349,10 @@ BOOLEAN MemFS3DefConstructorRet (
#else
#define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef,
#endif
- #else
+ #else
#define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef,
#define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef,
- #endif
+ #endif
#if OPTION_RDIMMS
#if OPTION_DDR2
#define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef,
@@ -2366,10 +2364,10 @@ BOOLEAN MemFS3DefConstructorRet (
#else
#define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef,
#endif
- #else
+ #else
#define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef,
#define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef,
- #endif
+ #endif
#if OPTION_SODIMMS
#define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef,
#define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef,
@@ -2389,7 +2387,7 @@ BOOLEAN MemFS3DefConstructorRet (
PLAT_SP_C32_FF_UDIMM3
PLAT_SP_C32_FF_RDIMM3
PLAT_SP_C32_FF_SDIMM3
- };
+ };
/*---------------------------------------------------------------------------------------------------
* PLATFORM-SPECIFIC CONFIGURATION
@@ -2402,7 +2400,7 @@ BOOLEAN MemFS3DefConstructorRet (
#if OPTION_UDIMMS
#if OPTION_DDR2
#define PSC_DR_UDIMM_DDR2 //MemAGetPsCfgUDr2
- #else
+ #else
#define PSC_DR_UDIMM_DDR2
#endif
#if OPTION_DDR3
@@ -2414,10 +2412,10 @@ BOOLEAN MemFS3DefConstructorRet (
#if OPTION_RDIMMS
#if OPTION_DDR2
#define PSC_DR_RDIMM_DDR2 MemAGetPsCfgRDr2,
- #else
+ #else
#define PSC_DR_RDIMM_DDR2
- #endif
- #if OPTION_DDR3
+ #endif
+ #if OPTION_DDR3
#define PSC_DR_RDIMM_DDR3 MemAGetPsCfgRDr3,
#else
#define PSC_DR_RDIMM_DDR3
@@ -2433,8 +2431,8 @@ BOOLEAN MemFS3DefConstructorRet (
#define PSC_DR_SODIMM_DDR3 //MemAGetPsCfgSDr3
#else
#define PSC_DR_SODIMM_DDR3
- #endif
- #endif
+ #endif
+ #endif
#endif
#if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
@@ -2471,14 +2469,14 @@ BOOLEAN MemFS3DefConstructorRet (
#endif
#if OPTION_DDR3
#define PSC_DA_UDIMM_DDR3 MemAGetPsCfgUDA3,
- #else
+ #else
#define PSC_DA_UDIMM_DDR3
- #endif
#endif
+ #endif
#if OPTION_RDIMMS
#if OPTION_DDR2
#define PSC_DA_RDIMM_DDR2
- #else
+ #else
#define PSC_DA_RDIMM_DDR2
#endif
#if OPTION_DDR3
@@ -2490,14 +2488,14 @@ BOOLEAN MemFS3DefConstructorRet (
#if OPTION_SODIMMS
#if OPTION_DDR2
#define PSC_DA_SODIMM_DDR2 MemAGetPsCfgSDA2,
- #else
+ #else
#define PSC_DA_SODIMM_DDR2
- #endif
+ #endif
#if OPTION_DDR3
#define PSC_DA_SODIMM_DDR3 MemAGetPsCfgSDA3,
- #else
+ #else
#define PSC_DA_SODIMM_DDR3
- #endif
+ #endif
#endif
#endif
#endif
@@ -2530,12 +2528,12 @@ BOOLEAN MemFS3DefConstructorRet (
#if OPTION_SODIMMS
#if OPTION_DDR2
#define PSC_HY_SODIMM_DDR2 //MemAGetPsCfgSHy2,
- #else
+ #else
#define PSC_HY_SODIMM_DDR2
- #endif
+ #endif
#if OPTION_DDR3
#define PSC_HY_SODIMM_DDR3 //MemAGetPsCfgSHy3,
- #else
+ #else
#define PSC_HY_SODIMM_DDR3
#endif
#endif
@@ -2627,28 +2625,28 @@ BOOLEAN MemFS3DefConstructorRet (
#ifndef PSC_DR_UDIMM_DDR2
#define PSC_DR_UDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_DR_RDIMM_DDR2
#define PSC_DR_RDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_DR_SODIMM_DDR2
#define PSC_DR_SODIMM_DDR2
- #endif
+ #endif
#ifndef PSC_DR_UDIMM_DDR3
#define PSC_DR_UDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_DR_RDIMM_DDR3
#define PSC_DR_RDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_DR_SODIMM_DDR3
#define PSC_DR_SODIMM_DDR3
- #endif
+ #endif
#ifndef PSC_RB_UDIMM_DDR2
#define PSC_RB_UDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_RB_RDIMM_DDR2
#define PSC_RB_RDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_RB_SODIMM_DDR2
#define PSC_RB_SODIMM_DDR2
#endif
@@ -2663,133 +2661,133 @@ BOOLEAN MemFS3DefConstructorRet (
#endif
#ifndef PSC_DA_UDIMM_DDR2
#define PSC_DA_UDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_DA_RDIMM_DDR2
#define PSC_DA_RDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_DA_SODIMM_DDR2
#define PSC_DA_SODIMM_DDR2
- #endif
+ #endif
#ifndef PSC_DA_UDIMM_DDR3
#define PSC_DA_UDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_DA_RDIMM_DDR3
#define PSC_DA_RDIMM_DDR3
#endif
#ifndef PSC_DA_SODIMM_DDR3
#define PSC_DA_SODIMM_DDR3
- #endif
+ #endif
#ifndef PSC_NI_UDIMM_DDR2
#define PSC_NI_UDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_NI_RDIMM_DDR2
#define PSC_NI_RDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_NI_SODIMM_DDR2
#define PSC_NI_SODIMM_DDR2
- #endif
+ #endif
#ifndef PSC_NI_UDIMM_DDR3
#define PSC_NI_UDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_NI_RDIMM_DDR3
#define PSC_NI_RDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_NI_SODIMM_DDR3
#define PSC_NI_SODIMM_DDR3
- #endif
+ #endif
#ifndef PSC_PH_UDIMM_DDR2
#define PSC_PH_UDIMM_DDR2
#endif
#ifndef PSC_PH_RDIMM_DDR2
#define PSC_PH_RDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_PH_SODIMM_DDR2
#define PSC_PH_SODIMM_DDR2
- #endif
+ #endif
#ifndef PSC_PH_UDIMM_DDR3
#define PSC_PH_UDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_PH_RDIMM_DDR3
- #define PSC_PH_RDIMM_DDR3
- #endif
+ #define PSC_PH_RDIMM_DDR3
+ #endif
#ifndef PSC_PH_SODIMM_DDR3
#define PSC_PH_SODIMM_DDR3
#endif
#ifndef PSC_HY_UDIMM_DDR2
- #define PSC_HY_UDIMM_DDR2
- #endif
+ #define PSC_HY_UDIMM_DDR2
+ #endif
#ifndef PSC_HY_RDIMM_DDR2
- #define PSC_HY_RDIMM_DDR2
- #endif
+ #define PSC_HY_RDIMM_DDR2
+ #endif
#ifndef PSC_HY_SODIMM_DDR2
- #define PSC_HY_SODIMM_DDR2
- #endif
+ #define PSC_HY_SODIMM_DDR2
+ #endif
#ifndef PSC_HY_UDIMM_DDR3
#define PSC_HY_UDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_HY_RDIMM_DDR3
#define PSC_HY_RDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_HY_SODIMM_DDR3
#define PSC_HY_SODIMM_DDR3
#endif
#ifndef PSC_LN_UDIMM_DDR2
#define PSC_LN_UDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_LN_RDIMM_DDR2
#define PSC_LN_RDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_LN_SODIMM_DDR2
#define PSC_LN_SODIMM_DDR2
- #endif
+ #endif
#ifndef PSC_LN_UDIMM_DDR3
#define PSC_LN_UDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_LN_RDIMM_DDR3
#define PSC_LN_RDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_LN_SODIMM_DDR3
#define PSC_LN_SODIMM_DDR3
- #endif
+ #endif
#ifndef PSC_OR_UDIMM_DDR2
#define PSC_OR_UDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_OR_RDIMM_DDR2
#define PSC_OR_RDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_OR_SODIMM_DDR2
#define PSC_OR_SODIMM_DDR2
- #endif
+ #endif
#ifndef PSC_OR_UDIMM_DDR3
#define PSC_OR_UDIMM_DDR3
#endif
#ifndef PSC_OR_RDIMM_DDR3
#define PSC_OR_RDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_OR_SODIMM_DDR3
#define PSC_OR_SODIMM_DDR3
- #endif
+ #endif
#ifndef PSC_C32_UDIMM_DDR3
#define PSC_C32_UDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_C32_RDIMM_DDR3
#define PSC_C32_RDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_ON_UDIMM_DDR2
#define PSC_ON_UDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_ON_RDIMM_DDR2
#define PSC_ON_RDIMM_DDR2
- #endif
+ #endif
#ifndef PSC_ON_SODIMM_DDR2
#define PSC_ON_SODIMM_DDR2
- #endif
+ #endif
#ifndef PSC_ON_UDIMM_DDR3
#define PSC_ON_UDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_ON_RDIMM_DDR3
#define PSC_ON_RDIMM_DDR3
- #endif
+ #endif
#ifndef PSC_ON_SODIMM_DDR3
#define PSC_ON_SODIMM_DDR3
#endif
@@ -2910,7 +2908,7 @@ BOOLEAN MemFS3DefConstructorRet (
#define PSC_TBL_OR_UDIMM3_WL_SEED_G34 &WLPass1SeedEntUG34,
extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUG34;
#define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34 &HWRxEnPass1SeedEntUG34,
- #endif
+ #endif
#endif
#if OPTION_RDIMMS
#if OPTION_C32_SOCKET_SUPPORT
@@ -2938,7 +2936,7 @@ BOOLEAN MemFS3DefConstructorRet (
#define PSC_TBL_OR_RDIMM3_WL_SEED_C32 &WLPass1SeedEntRC32,
extern PSC_TBL_ENTRY HWRxEnPass1SeedEntRC32;
#define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32 &HWRxEnPass1SeedEntRC32,
- #endif
+ #endif
#if OPTION_G34_SOCKET_SUPPORT
extern PSC_TBL_ENTRY MaxFreqTblEntRG34;
#define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 &MaxFreqTblEntRG34,
@@ -2964,7 +2962,7 @@ BOOLEAN MemFS3DefConstructorRet (
#define PSC_TBL_OR_RDIMM3_WL_SEED_G34 &WLPass1SeedEntRG34,
extern PSC_TBL_ENTRY HWRxEnPass1SeedEntRG34;
#define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34 &HWRxEnPass1SeedEntRG34,
- #endif
+ #endif
#endif
//#if OPTION_SODIMMS
//#endif
@@ -3016,7 +3014,7 @@ BOOLEAN MemFS3DefConstructorRet (
#define PSC_TBL_OR_LRDIMM3_WL_SEED_G34 &WLPass1SeedEntLRG34,
extern PSC_TBL_ENTRY HWRxEnPass1SeedEntLRG34;
#define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 &HWRxEnPass1SeedEntLRG34,
- #endif
+ #endif
#endif
extern PSC_TBL_ENTRY MR0WrTblEntry;
#define PSC_TBL_OR_MR0_WR &MR0WrTblEntry,
@@ -3072,22 +3070,22 @@ BOOLEAN MemFS3DefConstructorRet (
#endif
#ifndef PSC_TBL_OR_UDIMM3_ODT_PAT____G34
#define PSC_TBL_OR_UDIMM3_ODT_PAT____G34
- #endif
+ #endif
#ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
#define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
- #endif
+ #endif
#ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
#define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
#endif
#ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
#define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
- #endif
+ #endif
#ifndef PSC_TBL_OR_UDIMM3_SAO_AM3
#define PSC_TBL_OR_UDIMM3_SAO_AM3
#endif
#ifndef PSC_TBL_OR_UDIMM3_SAO_C32
#define PSC_TBL_OR_UDIMM3_SAO_C32
- #endif
+ #endif
#ifndef PSC_TBL_OR_UDIMM3_SAO_G34
#define PSC_TBL_OR_UDIMM3_SAO_G34
#endif
@@ -3535,7 +3533,7 @@ BOOLEAN MemFS3DefConstructorRet (
#endif
#ifndef PSC_FLOW_OR_LR_NLR
#define PSC_FLOW_OR_LR_NLR MEM_PSC_FLOW_DEFTRUE
- #endif
+ #endif
#ifndef PSC_FLOW_OR_S__
#define PSC_FLOW_OR_S__ MEM_PSC_FLOW_DEFTRUE
#endif
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryRecoveryInstall.h
index f5dea81..3b3be12 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionMemoryRecoveryInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryRecoveryInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionMsgBasedC1eInstall.h
index a64321e..b02f47e 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionMsgBasedC1eInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionMsgBasedC1eInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionPreserveMailboxInstall.h
index 2b40f77..d6de572 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionPreserveMailboxInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionPreserveMailboxInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionPstateHpcModeInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionPstateHpcModeInstall.h
index 061b6f5..4bef975 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionPstateHpcModeInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionPstateHpcModeInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_PSTATE_HPC_MODE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionPstateInstall.h
index 8ca835c..37ca9a2 100644
--- a/src/vendorcode/amd/agesa/f15/Include/OptionPstateInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionPstateInstall.h
@@ -39,7 +39,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
#ifndef _OPTION_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/Options.h b/src/vendorcode/amd/agesa/f15/Include/Options.h
index abb4a76..e981e92 100644
--- a/src/vendorcode/amd/agesa/f15/Include/Options.h
+++ b/src/vendorcode/amd/agesa/f15/Include/Options.h
@@ -38,7 +38,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
diff --git a/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h
index 38ec4ad..4c732e0 100644
--- a/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h
@@ -40,7 +40,6 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- *
***************************************************************************/
/*****************************************************************************
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f15/Legacy/agesa.inc
index 617be48..e2ed701 100644
--- a/src/vendorcode/amd/agesa/f15/Legacy/agesa.inc
+++ b/src/vendorcode/amd/agesa/f15/Legacy/agesa.inc
@@ -714,13 +714,13 @@ PCIe_PORT_DATA ENDS
;DDI channel lane mapping
-CHANNEL_MAPPING STRUCT ;
+CHANNEL_MAPPING STRUCT ;
Lane0 UINT8 ? ;
- ;IN UINT8 Lane0 :2; ;
+ ;IN UINT8 Lane0 :2; ;
;IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping")
;IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping")
;IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping")
-CHANNEL_MAPPING ENDS ;
+CHANNEL_MAPPING ENDS ;
CONN_CHANNEL_MAPPING UNION
ChannelMappingValue UINT8 ? ; < Raw lane mapping
@@ -998,7 +998,6 @@ GNB_CONFIGURATION STRUCT
;
GNB_CONFIGURATION ENDS
-
; ---------------------------------------------------------------------------
; MEMORY-SPECIFIC DATA STRUCTURES
@@ -1343,7 +1342,7 @@ CH_DEF_STRUCT STRUCT
CsPresentDCT UINT16 ? ; < For each bit n 0..7, 1 = Chip-select n is present
DimmMirrorPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is OnDimmMirror capable
DimmSpdCse UINT8 ? ; < For each bit n 0..7, 1 = DIMM n SPD checksum error
- DimmExclude UINT8 ? ; < For each bit n 0..7, 1 = DIMM n gets excluded
+ DimmExclude UINT8 ? ; < For each bit n 0..7, 1 = DIMM n gets excluded
DimmYr06 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's year code <= 2006
DimmWk2406 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
DimmPlPresent UINT8 ? ; < Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
@@ -1914,7 +1913,6 @@ MEM_ERROR_TRAINING_SEED_NOT_FOUND EQU 040D3500h ; < No training se
MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 EQU 040A1F00h ; < Heap allocation error for DMI table for DDR2
MEM_ERROR_UNSUPPORTED_DIMM_CONFIG EQU 04011400h ; < Dimm population is not supported
-
; ----------------------------------------------------------------------------
; *
; * END OF MEMORY-SPECIFIC DATA STRUCTURES
@@ -2388,7 +2386,6 @@ PLATFORM_CONFIGURATION ENDS
PROC_VERSION_LENGTH EQU 48
MAX_DIMMS_PER_SOCKET EQU 16
-
; Interface Parameter Structures
; DMI Type4 - Processor ID
TYPE4_PROC_ID STRUCT
@@ -2476,9 +2473,9 @@ TYPE16_DMI_INFO STRUCT
; < is used.
MemoryErrorCorrection DMI_T16_ERROR_CORRECTION ? ; < The primary hardware error correction or
; < detection method supported by this memory array.
- MaximumCapacity UINT32 ? ; < The maximum memory capacity, in kilobytes,
+ MaximumCapacity UINT32 ? ; < The maximum memory capacity, in kilobytes,
; < for the array.
- NumberOfMemoryDevices UINT16 ? ; < The number of slots or sockets available
+ NumberOfMemoryDevices UINT16 ? ; < The number of slots or sockets available
; < for memory devices in this array.
ExtMaxCapacity UINT64 ? ; < The maximum memory capacity, in bytes,
; < for this array.
@@ -2548,24 +2545,24 @@ DMI_T17_TYPE_DETAIL ENDS
; DMI Type 17 - Memory Device
TYPE17_DMI_INFO STRUCT
- TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; < Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; < The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device.
- DeviceSet UINT8 ? ; < Identifies when the Memory Device is one of a set of
+ TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
+ DataWidth UINT16 ? ; < Data Width, in bits, of this memory device.
+ MemorySize UINT16 ? ; < The size of the memory device.
+ FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device.
+ DeviceSet UINT8 ? ; < Identifies when the Memory Device is one of a set of
; < Memory Devices that must be populated with all devices of
; < the same type and size, and the set to which this device belongs.
DeviceLocator CHAR8 (8) DUP (?) ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
BankLocator CHAR8 (10) DUP (?) ; < The string number of the string that identifies the physically labeled bank where the memory device is located.
- MemoryType DMI_T17_MEMORY_TYPE ? ; < The type of memory used in this device.
- TypeDetail DMI_T17_TYPE_DETAIL {} ; < Additional detail on the memory device type
+ MemoryType DMI_T17_MEMORY_TYPE ? ; < The type of memory used in this device.
+ TypeDetail DMI_T17_TYPE_DETAIL {} ; < Additional detail on the memory device type
Speed UINT16 ? ; < Identifies the speed of the device, in megahertz (MHz).
ManufacturerIdCode UINT64 ? ; < Manufacturer ID code.
SerialNumber CHAR8 (9) DUP (?) ; < Serial Number.
PartNumber CHAR8 (19) DUP (?) ; < Part Number.
Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank.
ExtSize UINT32 ? ; < Extended Size.
- ConfigSpeed UINT16 ? ; < Configured memory clock speed
+ ConfigSpeed UINT16 ? ; < Configured memory clock speed
TYPE17_DMI_INFO ENDS
; Memory DMI Type 17 and 20 - for memory use
@@ -2601,18 +2598,18 @@ MEM_DMI_INFO ENDS
; DMI Type 19 - Memory Array Mapped Address
TYPE19_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes,
- ; < of a range of memory mapped to the
- ; < specified physical memory array.
- EndingAddr UINT32 ? ; < The physical ending address of the
- ; < last kilobyte of a range of addresses
- ; < mapped to the specified physical memory array.
- MemoryArrayHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the physical memory array to which this
- ; < address range is mapped.
- PartitionWidth UINT8 ? ; < Identifies the number of memory devices that
- ; < form a single row of memory for the address
- ; < partition defined by this structure.
+ StartingAddr UINT32 ? ; < The physical address, in kilobytes,
+ ; < of a range of memory mapped to the
+ ; < specified physical memory array.
+ EndingAddr UINT32 ? ; < The physical ending address of the
+ ; < last kilobyte of a range of addresses
+ ; < mapped to the specified physical memory array.
+ MemoryArrayHandle UINT16 ? ; < The handle, or instance number, associated
+ ; < with the physical memory array to which this
+ ; < address range is mapped.
+ PartitionWidth UINT8 ? ; < Identifies the number of memory devices that
+ ; < form a single row of memory for the address
+ ; < partition defined by this structure.
ExtStartingAddr UINT64 ? ; < The physical address, in bytes, of a range of
; < memory mapped to the specified Physical Memory Array.
ExtEndingAddr UINT64 ? ; < The physical address, in bytes, of a range of
@@ -2621,24 +2618,24 @@ TYPE19_DMI_INFO ENDS
; DMI Type 20 - Memory Device Mapped Address
TYPE20_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range
- ; < of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryDeviceHandle UINT16 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryArrayMappedAddressHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the Memory Array Mapped Address structure to
- ; < which this device address range is mapped.
- PartitionRowPosition UINT8 ? ; < Identifies the position of the referenced Memory
- ; < Device in a row of the address partition.
- InterleavePosition UINT8 ? ; < The position of the referenced Memory Device in
- ; < an interleave.
- InterleavedDataDepth UINT8 ? ; < The maximum number of consecutive rows from the
- ; < referenced Memory Device that are accessed in a
- ; < single interleaved transfer.
+ StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range
+ ; < of memory mapped to the referenced Memory Device.
+ EndingAddr UINT32 ? ; < The handle, or instance number, associated with
+ ; < the Memory Device structure to which this address
+ ; < range is mapped.
+ MemoryDeviceHandle UINT16 ? ; < The handle, or instance number, associated with
+ ; < the Memory Device structure to which this address
+ ; < range is mapped.
+ MemoryArrayMappedAddressHandle UINT16 ? ; < The handle, or instance number, associated
+ ; < with the Memory Array Mapped Address structure to
+ ; < which this device address range is mapped.
+ PartitionRowPosition UINT8 ? ; < Identifies the position of the referenced Memory
+ ; < Device in a row of the address partition.
+ InterleavePosition UINT8 ? ; < The position of the referenced Memory Device in
+ ; < an interleave.
+ InterleavedDataDepth UINT8 ? ; < The maximum number of consecutive rows from the
+ ; < referenced Memory Device that are accessed in a
+ ; < single interleaved transfer.
ExtStartingAddr UINT64 ? ; < The physical address, in bytes, of a range of
; < memory mapped to the referenced Memory Device.
ExtEndingAddr UINT64 ? ; < The physical ending address, in bytes, of the last of
@@ -2765,7 +2762,7 @@ AMD_POST_PARAMS ENDS
AMD_ENV_PARAMS STRUCT
StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- GnbEnvConfiguration GNB_ENV_CONFIGURATION {} ; < platform operational characteristics.
+ GnbEnvConfiguration GNB_ENV_CONFIGURATION {} ; < GNB configuration
FchInterface FCH_INTERFACE {} ; FCH configuration
AMD_ENV_PARAMS ENDS
@@ -2775,7 +2772,7 @@ AMD_ENV_PARAMS ENDS
; AmdInitMid param structure
AMD_MID_PARAMS STRUCT
StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
+ PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics
FchInterface FCH_INTERFACE {} ; FCH configuration
AMD_MID_PARAMS ENDS
diff --git a/src/vendorcode/amd/agesa/f15/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15/Lib/amdlib.c
index 1180ad2..a27dafa 100644
--- a/src/vendorcode/amd/agesa/f15/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f15/Lib/amdlib.c
@@ -43,7 +43,6 @@
******************************************************************************
*/
-
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
@@ -64,19 +63,16 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------------------
*/
-
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
-
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
-
BOOLEAN
STATIC
GetPciMmioAddress (
@@ -1269,7 +1265,6 @@ LibAmdGetPackageType (
* @param[out] TempDataMask typecast data
*/
-
VOID
STATIC
LibAmdGetDataFromPtr (
@@ -1311,7 +1306,6 @@ LibAmdGetDataFromPtr (
* @retval Width in number of bytes
*/
-
UINT8
LibAmdAccessWidth (
IN ACCESS_WIDTH AccessWidth
@@ -1343,6 +1337,7 @@ LibAmdAccessWidth (
}
return Width;
}
+
VOID
CpuidRead (
IN UINT32 CpuidFcnAddress,
@@ -1351,6 +1346,7 @@ CpuidRead (
{
__cpuid ((int *)Value, CpuidFcnAddress);
}
+
UINT8
ReadNumberOfCpuCores(
VOID
diff --git a/src/vendorcode/amd/agesa/f15/cpcar.inc b/src/vendorcode/amd/agesa/f15/cpcar.inc
index 544cc64..6045e13 100644
--- a/src/vendorcode/amd/agesa/f15/cpcar.inc
+++ b/src/vendorcode/amd/agesa/f15/cpcar.inc
@@ -464,7 +464,7 @@ ENDM
; settings for using cache with main memory.
;
; Inputs:
-; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
+; ESI - [31:24] flags; [15:8]= Node#; [7:0]= core#
; Outputs:
; none
; Destroyed:
@@ -726,7 +726,7 @@ ENDM
; settings for using cache with main memory.
;
; Inputs:
-; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
+; ESI - [31:24] flags; [15:8]= Node#; [7:0]= core#
; Outputs:
; none
; Destroyed:
@@ -905,7 +905,7 @@ ENDM
; settings for using cache with main memory.
;
; Inputs:
-; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
+; ESI - [31:24] flags; [15:8]= Node#; [7:0]= core#
; Outputs:
; none
; Destroyed:
@@ -1097,7 +1097,7 @@ ENDM
; settings for using cache with main memory.
;
; Inputs:
-; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
+; ESI - [31:24] flags; [15:8]= Node#; [7:0]= core#
; Outputs:
; none
; Destroyed:
diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc
index c88709c..c65c4c8 100644
--- a/src/vendorcode/amd/agesa/f15/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15/gcccar.inc
@@ -537,7 +537,6 @@ node_core_f10_AP:
node_core_f10_exit:
.endm
-
/*****************************************************************************
** Family 12h MACROS
*****************************************************************************/
@@ -860,8 +859,6 @@ fam14_disable_stack_hook_exit:
node_core_f14_exit:
.endm
-
-
/*****************************************************************************
** Family 15h MACROS
*****************************************************************************/
@@ -926,7 +923,6 @@ fam15_skipClearingBit4:
fam15_enable_stack_hook_exit:
.endm
-
/*****************************************************************************
*
* AMD_DISABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless
@@ -1010,7 +1006,6 @@ fam15_enable_stack_hook_exit:
fam15_disable_stack_hook_exit:
.endm
-
/*****************************************************************************
*
* GET_NODE_ID_CORE_ID_F15 Macro - Stackless
diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h
index a709274..97401d8 100644
--- a/src/vendorcode/amd/agesa/f15tn/AGESA.h
+++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h
@@ -13,7 +13,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -54,35 +54,35 @@
//
// AGESA BASIC CALLOUTS
-#define AGESA_MEM_RELEASE 0x00028000ul
+#define AGESA_MEM_RELEASE 0x00028000
// AGESA ADVANCED CALLOUTS, Processor
-#define AGESA_CHECK_UMA 0x00028100ul
-#define AGESA_DO_RESET 0x00028101ul
-#define AGESA_ALLOCATE_BUFFER 0x00028102ul
-#define AGESA_DEALLOCATE_BUFFER 0x00028103ul
-#define AGESA_LOCATE_BUFFER 0x00028104ul
-#define AGESA_RUNFUNC_ONAP 0x00028105ul
+#define AGESA_CHECK_UMA 0x00028100
+#define AGESA_DO_RESET 0x00028101
+#define AGESA_ALLOCATE_BUFFER 0x00028102
+#define AGESA_DEALLOCATE_BUFFER 0x00028103
+#define AGESA_LOCATE_BUFFER 0x00028104
+#define AGESA_RUNFUNC_ONAP 0x00028105
// AGESA ADVANCED CALLOUTS, HyperTransport
// AGESA ADVANCED CALLOUTS, Memory
-#define AGESA_READ_SPD 0x00028140ul
-#define AGESA_HOOKBEFORE_DRAM_INIT 0x00028141ul
-#define AGESA_HOOKBEFORE_DQS_TRAINING 0x00028142ul
-#define AGESA_READ_SPD_RECOVERY 0x00028143ul
-#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144ul
-#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY 0x00028145ul
+#define AGESA_READ_SPD 0x00028140
+#define AGESA_HOOKBEFORE_DRAM_INIT 0x00028141
+#define AGESA_HOOKBEFORE_DQS_TRAINING 0x00028142
+#define AGESA_READ_SPD_RECOVERY 0x00028143
+#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144
+#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY 0x00028145
// AGESA IDS CALLOUTS
-#define AGESA_GET_IDS_INIT_DATA 0x00028200ul
+#define AGESA_GET_IDS_INIT_DATA 0x00028200
// AGESA GNB CALLOUTS
-#define AGESA_GNB_PCIE_SLOT_RESET 0x00028301ul
-#define AGESA_GNB_GFX_GET_VBIOS_IMAGE 0x00028302ul
+#define AGESA_GNB_PCIE_SLOT_RESET 0x00028301
+#define AGESA_GNB_GFX_GET_VBIOS_IMAGE 0x00028302
// AGESA FCH CALLOUTS
-#define AGESA_FCH_OEM_CALLOUT 0x00028401ul
+#define AGESA_FCH_OEM_CALLOUT 0x00028401
//------------------------------------------------------------------------
//
@@ -118,16 +118,16 @@
#define HT_FREQUENCY_LIMIT_2200M 0x1FFF ///< Specifies a limit of no more than 2200 MHz HT frequency.
#define HT_FREQUENCY_LIMIT_2400M 0x3FFF ///< Specifies a limit of no more than 2400 MHz HT frequency.
#define HT_FREQUENCY_LIMIT_2600M 0x7FFF ///< Specifies a limit of no more than 2600 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_2800M 0x27FFFul ///< Specifies a limit of no more than 2800 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_3000M 0x67FFFul ///< Specifies a limit of no more than 3000 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_3200M 0xE7FFFul ///< Specifies a limit of no more than 3200 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_3600M 0x1E7FFFul
+#define HT_FREQUENCY_LIMIT_2800M 0x27FFF ///< Specifies a limit of no more than 2800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3000M 0x67FFF ///< Specifies a limit of no more than 3000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3200M 0xE7FFF ///< Specifies a limit of no more than 3200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3600M 0x1E7FFF
#define HT_FREQUENCY_LIMIT_MAX HT_FREQUENCY_LIMIT_3600M
-#define HT_FREQUENCY_NO_LIMIT 0xFFFFFFFFul ///< Specifies a no limit of HT frequency.
+#define HT_FREQUENCY_NO_LIMIT 0xFFFFFFFF ///< Specifies a no limit of HT frequency.
// Unit ID Clumping special values
-#define HT_CLUMPING_DISABLE 0x00000000ul
-#define HT_CLUMPING_NO_LIMIT 0xFFFFFFFFul
+#define HT_CLUMPING_DISABLE 0x00000000
+#define HT_CLUMPING_NO_LIMIT 0xFFFFFFFF
#define HT_LIST_TERMINAL 0xFF ///< End of list.
#define HT_LIST_MATCH_ANY 0xFE ///< Match Any value, used for Sockets, Links, IO Chain Depth.
@@ -138,33 +138,33 @@
// Event definitions.
// Coherent subfunction events
-#define HT_EVENT_COH_EVENTS 0x10001000ul
-#define HT_EVENT_COH_NO_TOPOLOGY 0x10011000ul ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY.
-#define HT_EVENT_COH_OBSOLETE000 0x10021000ul // No longer used.
-#define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000ul ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX.
-#define HT_EVENT_COH_NODE_DISCOVERED 0x10041000ul ///< See ::HT_EVENT_COH_NODE_DISCOVERED.
-#define HT_EVENT_COH_MPCAP_MISMATCH 0x10051000ul ///< See ::HT_EVENT_COH_MPCAP_MISMATCH.
+#define HT_EVENT_COH_EVENTS 0x10001000
+#define HT_EVENT_COH_NO_TOPOLOGY 0x10011000 ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY.
+#define HT_EVENT_COH_OBSOLETE000 0x10021000 // No longer used.
+#define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000 ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX.
+#define HT_EVENT_COH_NODE_DISCOVERED 0x10041000 ///< See ::HT_EVENT_COH_NODE_DISCOVERED.
+#define HT_EVENT_COH_MPCAP_MISMATCH 0x10051000 ///< See ::HT_EVENT_COH_MPCAP_MISMATCH.
// Non-coherent subfunction events
-#define HT_EVENT_NCOH_EVENTS 0x10002000ul
-#define HT_EVENT_NCOH_BUID_EXCEED 0x10012000ul ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED
-#define HT_EVENT_NCOH_OBSOLETE000 0x10022000ul // No longer used.
-#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000ul ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED.
-#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000ul ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED.
-#define HT_EVENT_NCOH_DEVICE_FAILED 0x10052000ul ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED
-#define HT_EVENT_NCOH_AUTO_DEPTH 0x10062000ul ///< See ::HT_EVENT_NCOH_AUTO_DEPTH
+#define HT_EVENT_NCOH_EVENTS 0x10002000
+#define HT_EVENT_NCOH_BUID_EXCEED 0x10012000 ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED
+#define HT_EVENT_NCOH_OBSOLETE000 0x10022000 // No longer used.
+#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000 ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED.
+#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000 ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED.
+#define HT_EVENT_NCOH_DEVICE_FAILED 0x10052000 ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED
+#define HT_EVENT_NCOH_AUTO_DEPTH 0x10062000 ///< See ::HT_EVENT_NCOH_AUTO_DEPTH
// Optimization subfunction events
-#define HT_EVENT_OPT_EVENTS 0x10003000ul
-#define HT_EVENT_OPT_REQUIRED_CAP_RETRY 0x10013000ul ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
-#define HT_EVENT_OPT_REQUIRED_CAP_GEN3 0x10023000ul ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
-#define HT_EVENT_OPT_UNUSED_LINKS 0x10033000ul ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS.
-#define HT_EVENT_OPT_LINK_PAIR_EXCEED 0x10043000ul ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED.
+#define HT_EVENT_OPT_EVENTS 0x10003000
+#define HT_EVENT_OPT_REQUIRED_CAP_RETRY 0x10013000 ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
+#define HT_EVENT_OPT_REQUIRED_CAP_GEN3 0x10023000 ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
+#define HT_EVENT_OPT_UNUSED_LINKS 0x10033000 ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS.
+#define HT_EVENT_OPT_LINK_PAIR_EXCEED 0x10043000 ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED.
// HW Fault events
-#define HT_EVENT_HW_EVENTS 0x10004000ul
-#define HT_EVENT_HW_SYNCFLOOD 0x10014000ul ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD.
-#define HT_EVENT_HW_HTCRC 0x10024000ul ///< See ::HT_EVENT_DATA_HW_HT_CRC.
+#define HT_EVENT_HW_EVENTS 0x10004000
+#define HT_EVENT_HW_SYNCFLOOD 0x10014000 ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD.
+#define HT_EVENT_HW_HTCRC 0x10024000 ///< See ::HT_EVENT_DATA_HW_HT_CRC.
// The Recovery HT component uses 0x10005000 for events.
// For consistency, we avoid that range here.
@@ -458,10 +458,10 @@ typedef struct {
*/
// BBHT subfunction events
-#define HT_EVENT_BB_EVENTS 0x10005000ul
-#define HT_EVENT_BB_BUID_EXCEED 0x10015000ul
-#define HT_EVENT_BB_DEVICE_FAILED 0x10055000ul
-#define HT_EVENT_BB_AUTO_DEPTH 0x10065000ul
+#define HT_EVENT_BB_EVENTS 0x10005000
+#define HT_EVENT_BB_BUID_EXCEED 0x10015000
+#define HT_EVENT_BB_DEVICE_FAILED 0x10055000
+#define HT_EVENT_BB_AUTO_DEPTH 0x10065000
/*----------------------------------------------------------------------------
* HT Recovery TYPEDEFS, STRUCTURES, ENUMS
@@ -728,16 +728,16 @@ typedef enum {
// Event definitions
-#define GNB_EVENT_INVALID_CONFIGURATION 0x20010000ul // User configuration invalid
-#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001ul // Requested lane allocation for PCIe port can not be supported
-#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION 0x20010002ul // Requested incorrect PCIe port device address
-#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION 0x20010003ul // Incorrect parameter in DDI link configuration
-#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION 0x20010004ul // Invalid with for PCIe port or DDI link
-#define GNB_EVENT_INVALID_LANES_CONFIGURATION 0x20010005ul // Lane double subscribe lanes
-#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION 0x20010006ul // Requested lane allocation for DDI link(s) can not be supported
-#define GNB_EVENT_LINK_TRAINING_FAIL 0x20020000ul // PCIe Link training fail
-#define GNB_EVENT_BROKEN_LANE_RECOVERY 0x20030000ul // Broken lane workaround applied to recover link training
-#define GNB_EVENT_GEN2_SUPPORT_RECOVERY 0x20040000ul // Scale back to GEN1 to recover link training
+#define GNB_EVENT_INVALID_CONFIGURATION 0x20010000 // User configuration invalid
+#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001 // Requested lane allocation for PCIe port can not be supported
+#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION 0x20010002 // Requested incorrect PCIe port device address
+#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION 0x20010003 // Incorrect parameter in DDI link configuration
+#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION 0x20010004 // Invalid with for PCIe port or DDI link
+#define GNB_EVENT_INVALID_LANES_CONFIGURATION 0x20010005 // Lane double subscribe lanes
+#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION 0x20010006 // Requested lane allocation for DDI link(s) can not be supported
+#define GNB_EVENT_LINK_TRAINING_FAIL 0x20020000 // PCIe Link training fail
+#define GNB_EVENT_BROKEN_LANE_RECOVERY 0x20030000 // Broken lane workaround applied to recover link training
+#define GNB_EVENT_GEN2_SUPPORT_RECOVERY 0x20040000 // Scale back to GEN1 to recover link training
#define DESCRIPTOR_TERMINATE_LIST 0x80000000ull
@@ -1328,12 +1328,12 @@ typedef struct {
#define MAX_PLATFORM_TYPES 16 ///< Platform types per system
-#define MCT_TRNG_KEEPOUT_START 0x00004000ul ///< base [39:8]
-#define MCT_TRNG_KEEPOUT_END 0x00007FFFul ///< base [39:8]
+#define MCT_TRNG_KEEPOUT_START 0x00004000 ///< base [39:8]
+#define MCT_TRNG_KEEPOUT_END 0x00007FFF ///< base [39:8]
-#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000ul ///< Uma Region is interleaved
-#define UMA_ATTRIBUTE_ON_DCT0 0x40000000ul ///< UMA resides on memory that belongs to DCT0
-#define UMA_ATTRIBUTE_ON_DCT1 0x20000000ul ///< UMA resides on memory that belongs to DCT1
+#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000 ///< Uma Region is interleaved
+#define UMA_ATTRIBUTE_ON_DCT0 0x40000000 ///< UMA resides on memory that belongs to DCT0
+#define UMA_ATTRIBUTE_ON_DCT1 0x20000000 ///< UMA resides on memory that belongs to DCT1
typedef UINT8 PSO_TABLE; ///< Platform Configuration Table
@@ -1516,18 +1516,18 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------
-#define SYS_CFG 0xC0010010ul
-#define TOP_MEM 0xC001001Aul
-#define TOP_MEM2 0xC001001Dul
-#define HWCR 0xC0010015ul
-#define NB_CFG 0xC001001Ful
-
-#define FS_BASE 0xC0000100ul
-#define IORR0_BASE 0xC0010016ul
-#define IORR0_MASK 0xC0010017ul
-#define BU_CFG 0xC0011023ul
-#define BU_CFG2 0xC001102Aul
-#define COFVID_STAT 0xC0010071ul
+#define SYS_CFG 0xC0010010
+#define TOP_MEM 0xC001001A
+#define TOP_MEM2 0xC001001D
+#define HWCR 0xC0010015
+#define NB_CFG 0xC001001F
+
+#define FS_BASE 0xC0000100
+#define IORR0_BASE 0xC0010016
+#define IORR0_MASK 0xC0010017
+#define BU_CFG 0xC0011023
+#define BU_CFG2 0xC001102A
+#define COFVID_STAT 0xC0010071
#define TSC 0x10
//-----------------------------------------------------------------------------
@@ -2174,102 +2174,102 @@ typedef union {
// AGESA MEMORY ERRORS
// AGESA_ALERT Memory Errors
-#define MEM_ALERT_USER_TMG_MODE_OVERRULED 0x04010000ul ///< TIMING_MODE_SPECIFIC is requested but
- ///< cannot be applied to current configurations.
-#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100ul ///< DIMM organization miss-match
-#define MEM_ALERT_BK_INT_DIS 0x04010200ul ///< Bank interleaving disable for internal issue
+#define MEM_ALERT_USER_TMG_MODE_OVERRULED 0x04010000 ///< TIMING_MODE_SPECIFIC is requested but
+ ///< cannot be applied to current configurations.
+#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100 ///< DIMM organization miss-match
+#define MEM_ALERT_BK_INT_DIS 0x04010200 ///< Bank interleaving disable for internal issue
// AGESA_ERROR Memory Errors
-#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300ul ///< No DQS Position window for RD DQS
-#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300ul ///< Small DQS Position window for RD DQS
-#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300ul ///< No DQS Position window for WR DQS
-#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300ul ///< Small DQS Position window for WR DQS
-#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500ul ///< DIMM sparing has not been enabled for an internal issues
-#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300ul ///< Receive Enable value is too large
-#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300ul ///< There is no DQS receiver enable window
-#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600ul ///< Time out when polling DramEnabled bit
-#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700ul ///< Time out when polling DctAccessDone bit
-#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800ul ///< Time out when polling SendCtrlWord bit
-#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900ul ///< Time out when polling PrefDramTrainMode bit
-#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00ul ///< Time out when polling EnterSelfRef bit
-#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00ul ///< Time out when polling FreqChgInProg bit
-#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00ul ///< Time out when polling ExitSelfRef bit
-#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00ul ///< Time out when polling SendMrsCmd bit
-#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00ul ///< Time out when polling SendZQCmd bit
-#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00ul ///< Time out when polling DctExtraAccessDone bit
-#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00ul ///< Time out when polling MemClrBusy bit
-#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00ul ///< Time out when polling MemCleared bit
-#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000ul ///< Time out when polling FlushWr bit
-#define MEM_ERROR_NBPSTATE_TRANSITION_TIME_OUT 0x04012600ul ///< Time out when polling CurNBPstate bit
-#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300ul ///< Fail to find pass during Max Rd Latency training
-#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300ul ///< Fail to launch training code on an AP
-#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300ul ///< Fail to finish parallel training
-#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100ul ///< No address mapping found for a dimm
-#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT 0x040A0300ul ///< There is no DQS receiver enable window and the value is equal to the largest value
-#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300ul ///< Receive Enable value is too large and is 1 less than limit
-#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR 0x04011200ul ///< SPD Checksum error for NV_SPDCHK_RESTRT
-#define MEM_ERROR_NO_CHIPSELECT 0x04011300ul ///< No chipselects found
-#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500ul ///< Unbuffered dimm is not supported at 333MHz
-#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300ul ///< Returned PRE value during write levelizzation was out of range
-#define MEM_ERROR_LR_IBT_NOT_FOUND 0x04013500ul ///< No LR dimm IBT value is found
-#define MEM_ERROR_MR0_NOT_FOUND 0x04023500ul ///< No MR0 value is found
-#define MEM_ERROR_ODT_PATTERN_NOT_FOUND 0x04033500ul ///< No odt pattern value is found
-#define MEM_ERROR_RC2_IBT_NOT_FOUND 0x04043500ul ///< No RC2 IBT value is found
-#define MEM_ERROR_RC10_OP_SPEED_NOT_FOUND 0x04053500ul ///< No RC10 op speed is found
-#define MEM_ERROR_RTT_NOT_FOUND 0x04063500ul ///< No RTT value is found
-#define MEM_ERROR_P2D_NOT_FOUND 0x04073500ul ///< No 2D training config value is found
-#define MEM_ERROR_SAO_NOT_FOUND 0x04083500ul ///< No slow access mode, Address timing and Output driver compensation value is found
-#define MEM_ERROR_CLK_DIS_MAP_NOT_FOUND 0x04093500ul ///< No CLK disable map is found
-#define MEM_ERROR_CKE_TRI_MAP_NOT_FOUND 0x040A3500ul ///< No CKE tristate map is found
-#define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND 0x040B3500ul ///< No ODT tristate map is found
-#define MEM_ERROR_CS_TRI_MAP_NOT_FOUND 0x040C3500ul ///< No CS tristate map is found
-#define MEM_ERROR_TRAINING_SEED_NOT_FOUND 0x040D3500ul ///< No training seed is found
+#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300 ///< No DQS Position window for RD DQS
+#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300 ///< Small DQS Position window for RD DQS
+#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300 ///< No DQS Position window for WR DQS
+#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300 ///< Small DQS Position window for WR DQS
+#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500 ///< DIMM sparing has not been enabled for an internal issues
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300 ///< Receive Enable value is too large
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300 ///< There is no DQS receiver enable window
+#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600 ///< Time out when polling DramEnabled bit
+#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700 ///< Time out when polling DctAccessDone bit
+#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800 ///< Time out when polling SendCtrlWord bit
+#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900 ///< Time out when polling PrefDramTrainMode bit
+#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00 ///< Time out when polling EnterSelfRef bit
+#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00 ///< Time out when polling FreqChgInProg bit
+#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00 ///< Time out when polling ExitSelfRef bit
+#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00 ///< Time out when polling SendMrsCmd bit
+#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00 ///< Time out when polling SendZQCmd bit
+#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00 ///< Time out when polling DctExtraAccessDone bit
+#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00 ///< Time out when polling MemClrBusy bit
+#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00 ///< Time out when polling MemCleared bit
+#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000 ///< Time out when polling FlushWr bit
+#define MEM_ERROR_NBPSTATE_TRANSITION_TIME_OUT 0x04012600 ///< Time out when polling CurNBPstate bit
+#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300 ///< Fail to find pass during Max Rd Latency training
+#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300 ///< Fail to launch training code on an AP
+#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300 ///< Fail to finish parallel training
+#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100 ///< No address mapping found for a dimm
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT 0x040A0300 ///< There is no DQS receiver enable window and the value is equal to the largest value
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300 ///< Receive Enable value is too large and is 1 less than limit
+#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR 0x04011200 ///< SPD Checksum error for NV_SPDCHK_RESTRT
+#define MEM_ERROR_NO_CHIPSELECT 0x04011300 ///< No chipselects found
+#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500 ///< Unbuffered dimm is not supported at 333MHz
+#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300 ///< Returned PRE value during write levelizzation was out of range
+#define MEM_ERROR_LR_IBT_NOT_FOUND 0x04013500 ///< No LR dimm IBT value is found
+#define MEM_ERROR_MR0_NOT_FOUND 0x04023500 ///< No MR0 value is found
+#define MEM_ERROR_ODT_PATTERN_NOT_FOUND 0x04033500 ///< No odt pattern value is found
+#define MEM_ERROR_RC2_IBT_NOT_FOUND 0x04043500 ///< No RC2 IBT value is found
+#define MEM_ERROR_RC10_OP_SPEED_NOT_FOUND 0x04053500 ///< No RC10 op speed is found
+#define MEM_ERROR_RTT_NOT_FOUND 0x04063500 ///< No RTT value is found
+#define MEM_ERROR_P2D_NOT_FOUND 0x04073500 ///< No 2D training config value is found
+#define MEM_ERROR_SAO_NOT_FOUND 0x04083500 ///< No slow access mode, Address timing and Output driver compensation value is found
+#define MEM_ERROR_CLK_DIS_MAP_NOT_FOUND 0x04093500 ///< No CLK disable map is found
+#define MEM_ERROR_CKE_TRI_MAP_NOT_FOUND 0x040A3500 ///< No CKE tristate map is found
+#define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND 0x040B3500 ///< No ODT tristate map is found
+#define MEM_ERROR_CS_TRI_MAP_NOT_FOUND 0x040C3500 ///< No CS tristate map is found
+#define MEM_ERROR_TRAINING_SEED_NOT_FOUND 0x040D3500 ///< No training seed is found
// AGESA_WARNING Memory Errors
-#define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600ul ///< QR DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600ul ///< U DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600ul ///< SO-DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600ul ///< x4 DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600ul ///< R DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_LRDIMM 0x04061600ul ///< LR DIMMs detected but not supported
-#define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700ul ///< Processor is not capable for EMP
-#define MEM_WARNING_EMP_CONFLICT 0x04021700ul ///< EMP cannot be enabled if channel interleaving,
-#define MEM_WARNING_EMP_NOT_ENABLED 0x04031700ul ///< Memory size is not power of two.
-#define MEM_WARNING_ECC_DIS 0x04041700ul ///< ECC has been disabled as a result of an internal issue
-#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800ul ///< Performance has been enabled, but battery life is preferred.
- ///< bank interleaving, or bank swizzle is enabled.
-#define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900ul ///< No Trc timing value found in SPD of a dimm.
-#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000ul ///< Node Interleaveing Requested, but could not be enabled
-#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100ul ///< Channel Interleaveing Requested, but could not be enabled
-#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200ul ///< Bank Interleaveing Requested, but could not be enabled
-#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300ul ///< Voltage 1.35 determined, but could not be supported
-#define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO 0x04012400ul ///< DDR3 voltage initial value is not 0
-#define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO 0x04012500ul ///< Cannot find a commonly supported VDDIO
+#define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600 ///< QR DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600 ///< U DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600 ///< SO-DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600 ///< x4 DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600 ///< R DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_LRDIMM 0x04061600 ///< LR DIMMs detected but not supported
+#define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700 ///< Processor is not capable for EMP
+#define MEM_WARNING_EMP_CONFLICT 0x04021700 ///< EMP cannot be enabled if channel interleaving,
+#define MEM_WARNING_EMP_NOT_ENABLED 0x04031700 ///< Memory size is not power of two.
+#define MEM_WARNING_ECC_DIS 0x04041700 ///< ECC has been disabled as a rest of an internal issue
+#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800 ///< Performance has been enabled, but battery life is preferred.
+ ///< bank interleaving, or bank swizzle is enabled.
+#define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900 ///< No Trc timing value found in SPD of a dimm.
+#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000 ///< Node Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100 ///< Channel Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200 ///< Bank Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported
+#define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO 0x04012400 ///< DDR3 voltage initial value is not 0
+#define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO 0x04012500 ///< Cannot find a commonly supported VDDIO
// AGESA_FATAL Memory Errors
-#define MEM_ERROR_MINIMUM_MODE 0x04011A00ul ///< Running in minimum mode
-#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00ul ///< DIMM modules are miss-matched
-#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00ul ///< No DIMMs have been found
-#define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00ul ///< DIMM clocks miss-matched
-#define MEM_ERROR_NO_CYC_TIME 0x04011E00ul ///< No cycle time found
-#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00ul ///< Heap allocation error with dynamic storing of trained timings
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00ul ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00ul ///< Heap allocation error with REMOTE_TRAINING_ENV
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00ul ///< Heap allocation error for SPD data
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00ul ///< Heap allocation error for RECEIVED_DATA during parallel training
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00ul ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00ul ///< Heap allocation error for Training Data
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00ul ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK
-#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300ul ///< No Constructor for DIMM Identify
-#define MEM_ERROR_VDDIO_UNSUPPORTED 0x04022500ul ///< VDDIO of the dimms on the board is not supported
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_2D 0x040B1F00ul ///< Heap allocation error for 2D training data
-#define MEM_ERROR_HEAP_DEALLOCATE_FOR_2D 0x040C1F00ul ///< Heap de-allocation error for 2D training data
+#define MEM_ERROR_MINIMUM_MODE 0x04011A00 ///< Running in minimum mode
+#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00 ///< DIMM modules are miss-matched
+#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00 ///< No DIMMs have been found
+#define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00 ///< DIMM clocks miss-matched
+#define MEM_ERROR_NO_CYC_TIME 0x04011E00 ///< No cycle time found
+#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00 ///< Heap allocation error with dynamic storing of trained timings
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00 ///< Heap allocation error for SPD data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00 ///< Heap allocation error for RECEIVED_DATA during parallel training
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00 ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00 ///< Heap allocation error for Training Data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00 ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK
+#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300 ///< No Constructor for DIMM Identify
+#define MEM_ERROR_VDDIO_UNSUPPORTED 0x04022500 ///< VDDIO of the dimms on the board is not supported
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_2D 0x040B1F00 ///< Heap allocation error for 2D training data
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR_2D 0x040C1F00 ///< Heap de-allocation error for 2D training data
// AGESA_CRITICAL Memory Errors
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00ul ///< Heap allocation error for DMI table for DDR3
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00ul ///< Heap allocation error for DMI table for DDR2
-#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400ul ///< Dimm population is not supported
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY 0x040D1F00ul ///< Heap allocation error for CRAT memory affinity info
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00 ///< Heap allocation error for DMI table for DDR3
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00 ///< Heap allocation error for DMI table for DDR2
+#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400 ///< Dimm population is not supported
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY 0x040D1F00 ///< Heap allocation error for CRAT memory affinity info
@@ -2293,31 +2293,31 @@ typedef union {
// CPU Event definitions.
// Defines used to filter CPU events based on functional blocks
-#define CPU_EVENT_PM_EVENT_MASK 0xFF00FF00ul
-#define CPU_EVENT_PM_EVENT_CLASS 0x08000400ul
+#define CPU_EVENT_PM_EVENT_MASK 0xFF00FF00
+#define CPU_EVENT_PM_EVENT_CLASS 0x08000400
//================================================================
// CPU General events
// Heap allocation (AppFunction = 01h)
-#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT 0x08000100ul
-#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED 0x08010100ul
-#define CPU_ERROR_HEAP_IS_FULL 0x08020100ul
-#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED 0x08030100ul
-#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT 0x08040100ul
+#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT 0x08000100
+#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED 0x08010100
+#define CPU_ERROR_HEAP_IS_FULL 0x08020100
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED 0x08030100
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT 0x08040100
// BrandId (AppFunction = 02h)
-#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE 0x08000200ul
+#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE 0x08000200
// Micro code patch (AppFunction = 03h)
-#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED 0x08000300ul
+#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED 0x08000300
// Power management (AppFunction = 04h)
-#define CPU_EVENT_PM_PSTATE_OVERCURRENT 0x08000400ul
-#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT 0x08010400ul
-#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE 0x08020400ul
-#define CPU_ERROR_PM_NB_PSTATE_MISMATCH 0x08030400ul
+#define CPU_EVENT_PM_PSTATE_OVERCURRENT 0x08000400
+#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT 0x08010400
+#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE 0x08020400
+#define CPU_ERROR_PM_NB_PSTATE_MISMATCH 0x08030400
// Other CPU events (AppFunction = 05h)
-#define CPU_EVENT_BIST_ERROR 0x08000500ul
-#define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY 0x08010500ul
-#define CPU_EVENT_STACK_REENTRY 0x08020500ul
-#define CPU_EVENT_CORE_NOT_IDENTIFIED 0x08030500ul
+#define CPU_EVENT_BIST_ERROR 0x08000500
+#define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY 0x08010500
+#define CPU_EVENT_STACK_REENTRY 0x08020500
+#define CPU_EVENT_CORE_NOT_IDENTIFIED 0x08030500
//=================================================================
// CPU Feature events
@@ -2329,11 +2329,11 @@ typedef union {
// AGESA_CACHE_START_ADDRESS_LESS_D0000 2105
// AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106
// AGESA_DEALLOCATE_CACHE_REGIONS 2107
-#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR 0x08002100ul
+#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR 0x08002100
// Core Leveling (AppFunction = 22h)
-#define CPU_WARNING_ADJUSTED_LEVELING_MODE 0x08002200ul
+#define CPU_WARNING_ADJUSTED_LEVELING_MODE 0x08002200
// HT Assist (AppFunction = 23h)
-#define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG 0x08002300ul
+#define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG 0x08002300
// CPU Build Configuration structures and definitions
@@ -2343,18 +2343,18 @@ typedef struct {
IN UINT64 MsrData; ///< MTRR Settings
} AP_MTRR_SETTINGS;
-#define AMD_AP_MTRR_FIX64k_00000 0x00000250ul
-#define AMD_AP_MTRR_FIX16k_80000 0x00000258ul
-#define AMD_AP_MTRR_FIX16k_A0000 0x00000259ul
-#define AMD_AP_MTRR_FIX4k_C0000 0x00000268ul
-#define AMD_AP_MTRR_FIX4k_C8000 0x00000269ul
-#define AMD_AP_MTRR_FIX4k_D0000 0x0000026Aul
-#define AMD_AP_MTRR_FIX4k_D8000 0x0000026Bul
-#define AMD_AP_MTRR_FIX4k_E0000 0x0000026Cul
-#define AMD_AP_MTRR_FIX4k_E8000 0x0000026Dul
-#define AMD_AP_MTRR_FIX4k_F0000 0x0000026Eul
-#define AMD_AP_MTRR_FIX4k_F8000 0x0000026Ful
-#define CPU_LIST_TERMINAL 0xFFFFFFFFul
+#define AMD_AP_MTRR_FIX64k_00000 0x00000250
+#define AMD_AP_MTRR_FIX16k_80000 0x00000258
+#define AMD_AP_MTRR_FIX16k_A0000 0x00000259
+#define AMD_AP_MTRR_FIX4k_C0000 0x00000268
+#define AMD_AP_MTRR_FIX4k_C8000 0x00000269
+#define AMD_AP_MTRR_FIX4k_D0000 0x0000026A
+#define AMD_AP_MTRR_FIX4k_D8000 0x0000026B
+#define AMD_AP_MTRR_FIX4k_E0000 0x0000026C
+#define AMD_AP_MTRR_FIX4k_E8000 0x0000026D
+#define AMD_AP_MTRR_FIX4k_F0000 0x0000026E
+#define AMD_AP_MTRR_FIX4k_F8000 0x0000026F
+#define CPU_LIST_TERMINAL 0xFFFFFFFF
/// Data structure for the Mapping Item between Unified ID for IDS Setup Option
/// and the option value.
@@ -2419,8 +2419,6 @@ typedef enum {
AMD_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D00B buffer handle to CRAT function
AMD_ACPI_CDIT_BUFFER_HANDLE ///< Assign 0x000D00C buffer handle to CDIT function
} AMD_BUFFER_HANDLE;
-
-
/************************************************************************
*
* AGESA interface Call-Out function prototypes
@@ -3687,5 +3685,4 @@ typedef enum {
#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1)
-
#endif // _AGESA_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h b/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h
index 274ef14..f37bc14 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h
@@ -16,7 +16,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/GnbInterface.h b/src/vendorcode/amd/agesa/f15tn/Include/GnbInterface.h
index 3f4bbab..eee9da0 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/GnbInterface.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/GnbInterface.h
@@ -13,9 +13,9 @@
*
*/
/*
-*****************************************************************************
-*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ *****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,9 +39,10 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
+ *
+ ****************************************************************************
+ *
+ */
#ifndef _GNBINTERFACE_H_
#define _GNBINTERFACE_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h b/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h
index d762022..2033a8e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h
@@ -17,7 +17,7 @@
/*
******************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,6 +41,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
******************************************************************************
*/
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/Ids.h b/src/vendorcode/amd/agesa/f15tn/Include/Ids.h
index abbb6d4..03c197a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/Ids.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/Ids.h
@@ -13,7 +13,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -52,8 +52,8 @@
#define TRUE 1
// Proto type for optionsids.h
typedef UINT32 IDS_STATUS; ///< Status of IDS function.
-#define IDS_SUCCESS ((IDS_STATUS) 0x00000000ul) ///< IDS Function is Successful.
-#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFFul) ///< IDS Function is not existed.
+#define IDS_SUCCESS ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful.
+#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed.
#define IDS_STRINGIZE(a) #a ///< for define stringize macro
#ifndef IDS_DEADLOOP
@@ -363,7 +363,7 @@ typedef enum { //vv- for debug reference only
#ifdef STOP_CODE
#undef STOP_CODE
#endif
- #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
(((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
@@ -404,7 +404,7 @@ typedef enum { //vv- for debug reference only
#ifdef STOP_CODE
#undef STOP_CODE
#endif
- #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
(((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
@@ -515,8 +515,8 @@ typedef enum { //vv- for debug reference only
**/
// Heap debug feature
-#define SENTINEL_BEFORE_VALUE 0x64616548ul // "Head"
-#define SENTINEL_AFTER_VALUE 0x6C696154ul // "Tail"
+#define SENTINEL_BEFORE_VALUE 0x64616548 // "Head"
+#define SENTINEL_AFTER_VALUE 0x6C696154 // "Tail"
#if IDSOPT_IDS_ENABLED == TRUE
#if IDSOPT_HEAP_CHECKING == TRUE
#define SIZE_OF_SENTINEL 4
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h
index e88d35b..d21ab7f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h
index 088d303..69a8be8 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -114,7 +114,6 @@
#endif
#endif
-
#endif
#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h
index b2fa7d6..959c413 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -118,7 +118,6 @@
#undef F14_ON_CPB_SUPPORT
#define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport},
#endif
-
#endif
#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h
index f00ee23..6ffca5b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -102,7 +102,6 @@
#undef F15_TN_CPU_CFOH_SUPPORT
#define F15_TN_CPU_CFOH_SUPPORT {AMD_FAMILY_15_TN, &F15TnCacheFlushOnHalt},
#endif
-
#endif
#endif
#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCoreLevelingInstall.h
index 855930a..3d7793a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCoreLevelingInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCoreLevelingInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -92,13 +92,11 @@
#undef F15_OR_CPU_CORELEVELING_SUPPORT
#define F15_OR_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_OR, &F15OrCoreLeveling},
#endif
-
#if (OPTION_FAMILY15H_TN == TRUE)
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15TnCoreLeveling;
#undef F15_TN_CPU_CORELEVELING_SUPPORT
#define F15_TN_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_TN, &F15TnCoreLeveling},
#endif
-
#endif
#endif
#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuFamiliesInstall.h
index fb4da3f..f68b702 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuFamiliesInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuFamiliesInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -348,7 +348,7 @@
#endif
#endif
- #define PCI_MMIO_ALIGNMENT ((0x100000ul * CFG_PCI_MMIO_SIZE) - 1)
+ #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
// If the base is not aligned according to size, break the build.
#if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
#error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
@@ -397,7 +397,6 @@ CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
OPT_F12_ID_TABLE
OPT_F14_ID_TABLE
OPT_F15_ID_TABLE
-
};
CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuFeaturesInstall.h
index 50829bd..2adc97c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuFeaturesInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuFeaturesInstall.h
@@ -13,7 +13,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h
index 73e5041..4fa4219 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h
index d1e5c5b..6016ab6 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h
@@ -13,7 +13,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -837,8 +837,6 @@ extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled;
#define OPT_F15_TN_ID
#endif // defined (OPTION_FAMILY15H_TN)
-
-
/*
* Install unknown family 15h support
*/
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h
index bf4c208..716f21f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h
@@ -13,30 +13,31 @@
*/
/*********************************************************************************
;
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
;*********************************************************************************/
#ifndef _OPTION_FCH_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionGnb.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionGnb.h
index d439fc4..aee92c0 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionGnb.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionGnb.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -38,6 +38,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
******************************************************************************
*/
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h
index 022eee3..a2d83f2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -338,9 +338,9 @@
#ifndef OPTION_PCIE_EARLY_INIT
#define OPTION_PCIE_EARLY_INIT TRUE
#endif
- #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtEarly;
- #define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtEarly},
+ #define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly},
#else
#define OPTION_PCIEINITATEARLY_ENTRY
#endif
@@ -406,9 +406,9 @@
#ifndef OPTION_GFX_POST_INIT
#define OPTION_GFX_POST_INIT TRUE
#endif
- #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxInitAtPost;
- #define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxInitAtPost},
+ #define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost},
#else
#define OPTION_GFXINITATPOST_ENTRY
#endif
@@ -423,9 +423,9 @@
#ifndef OPTION_NB_POST_INIT
#define OPTION_NB_POST_INIT TRUE
#endif
- #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtPost;
- #define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtPost},
+ #define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost},
#else
#define OPTION_NBINITATPOST_ENTRY
#endif
@@ -436,13 +436,13 @@
#define OPTION_GNBPOSTINTERFACETN_ENTRY
#endif
- //---------------------------------------------------------------------------------------------------
+ //---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POST_EALRY_INIT
#define OPTION_PCIE_POST_EALRY_INIT TRUE
#endif
- #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtPostEarly;
- #define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtPostEarly},
+ #define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly},
#else
#define OPTION_PCIEINITATPOSTEARLY_ENTRY
#endif
@@ -457,9 +457,9 @@
#ifndef OPTION_PCIE_POST_INIT
#define OPTION_PCIE_POST_INIT TRUE
#endif
- #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtPost;
- #define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtPost},
+ #define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost},
#else
#define OPTION_PCIEINITATPOST_ENTRY
#endif
@@ -494,9 +494,9 @@
#ifndef OPTION_FUSE_TABLE_INIT
#define OPTION_FUSE_TABLE_INIT TRUE
#endif
- #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbFuseTableFeature;
- #define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbFuseTableFeature},
+ #define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature},
#else
#define OPTION_NBFUSETABLEFEATURE_ENTRY
#endif
@@ -504,9 +504,9 @@
#ifndef OPTION_NB_ENV_INIT
#define OPTION_NB_ENV_INIT TRUE
#endif
- #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtEnv;
- #define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtEnv},
+ #define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv},
#else
#define OPTION_NBINITATENVT_ENTRY
#endif
@@ -532,9 +532,9 @@
#ifndef OPTION_GFX_ENV_INIT
#define OPTION_GFX_ENV_INIT TRUE
#endif
- #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxInitAtEnvPost;
- #define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxInitAtEnvPost},
+ #define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost},
#else
#define OPTION_GFXINITATENVPOST_ENTRY
#endif
@@ -565,9 +565,9 @@
#ifndef OPTION_PCIE_ENV_INIT
#define OPTION_PCIE_ENV_INIT TRUE
#endif
- #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtEnv;
- #define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtEnv},
+ #define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv},
#else
#define OPTION_PCIEINITATENV_ENTRY
#endif
@@ -620,9 +620,9 @@
#ifndef OPTION_NB_LCLK_DPM_INIT
#define OPTION_NB_LCLK_DPM_INIT TRUE
#endif
- #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbLclkDpmFeature;
- #define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbLclkDpmFeature},
+ #define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature},
#else
#define OPTION_NBLCLKDPMFEATURE_ENTRY
#endif
@@ -640,9 +640,9 @@
#ifndef OPTION_GFX_MID_INIT
#define OPTION_GFX_MID_INIT TRUE
#endif
- #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxInitAtMidPost;
- #define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxInitAtMidPost},
+ #define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost},
#else
#define OPTION_GFXINITATMIDPOST_ENTRY
#endif
@@ -656,9 +656,9 @@
#ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
#define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
#endif
- #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry;
- #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxIntegratedInfoTableEntry},
+ #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry},
#else
#define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
#endif
@@ -673,9 +673,9 @@
#ifndef OPTION_PCIe_MID_INIT
#define OPTION_PCIe_MID_INIT TRUE
#endif
- #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtMid;
- #define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtMid},
+ #define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid},
#else
#define OPTION_PCIEINITATMID_ENTRY
#endif
@@ -690,9 +690,9 @@
#ifndef OPTION_NB_MID_INIT
#define OPTION_NB_MID_INIT TRUE
#endif
- #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtLatePost;
- #define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtLatePost},
+ #define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost},
#else
#define OPTION_NBINITATLATEPOST_ENTRY
#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h
index d6055bc..6b226d9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -303,7 +303,7 @@
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
- #if ((OPTION_FAMILY15H_TN == TRUE) )
+ #if ((OPTION_FAMILY15H_TN == TRUE))
#undef OPTION_HT_INIIT_RESET_ENTRY
#undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY NULL
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h
index 83c28d2..9276281 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h
@@ -13,7 +13,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h
index b94b043..938a379 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h
index 981e7c9..ad230c4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h
index 017c981..cb46946 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -38,6 +38,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
******************************************************************************
*/
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h
index f165704..51847bb 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -504,7 +504,6 @@ BOOLEAN MemFS3DefConstructorRet (
#define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
#endif
-
#if (OPTION_DDR3 == TRUE)
extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal;
extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3;
@@ -1753,7 +1752,6 @@ BOOLEAN MemFS3DefConstructorRet (
TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
TECH_TRAIN_MAX_RD_LAT_DDR3,
TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
-
};
#define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
#if (OPTION_MEMCTLR_DA)
@@ -1925,7 +1923,7 @@ BOOLEAN MemFS3DefConstructorRet (
#undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
#define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect
#else
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+ #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
#define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect
#else
#define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
@@ -4633,9 +4631,9 @@ BOOLEAN MemFS3DefConstructorRet (
*---------------------------------------------------------------------------------------------------
*/
#if (OPTION_LRDIMMS == TRUE)
- #if ((OPTION_MEMCTLR_OR == TRUE)
+ #if ((OPTION_MEMCTLR_OR == TRUE))
#define MEM_TECH_FEATURE_LRDIMM_INIT &MemTLrdimmConstructor3
- #else //#if ((OPTION_MEMCTLR_OR == FALSE)
+ #else //#if ((OPTION_MEMCTLR_OR == FALSE))
#define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef
#endif
#else //#if (OPTION_LRDIMMS == FALSE)
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecoveryInstall.h
index 4740035..b79bc67 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecoveryInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecoveryInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h
index 986690b..3d6303e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMultiSocket.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMultiSocket.h
index d343bd9..58014a5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMultiSocket.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMultiSocket.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -38,6 +38,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
******************************************************************************
*/
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h
index d42175c..8b74b24 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h
index 6b7f7f7..071e3ed 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h
index 18f22ac..8c3cf13 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/Options.h b/src/vendorcode/amd/agesa/f15tn/Include/Options.h
index 9e4bdf2..e981e92 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/Options.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/Options.h
@@ -9,11 +9,11 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
- * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ * @e \$Revision: 53142 $ @e \$Date: 2011-05-16 12:01:19 -0600 (Mon, 16 May 2011) $
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionsHt.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionsHt.h
index 291bd3d..ddcc024 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionsHt.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionsHt.h
@@ -10,12 +10,12 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
- * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,6 +39,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
******************************************************************************
*/
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionsPage.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionsPage.h
index 1040912..546acf7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionsPage.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionsPage.h
@@ -17,7 +17,7 @@
/*
******************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,6 +41,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
******************************************************************************
*/
@@ -136,7 +137,6 @@
* @li @e BLDCFG_PSTATE_HPC_MODE @n
* This option enables PStates high performance computing mode (HPC mode)
*
- *
* @anchor BLDOPT_REMOVE_SRAT
* @li @e BLDOPT_REMOVE_SRAT @n
* This option removes the code that generates the SRAT tables used in performance
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h
index eca567b..144a454 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h
@@ -15,7 +15,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -215,7 +215,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
#endif
#endif
-
#ifdef INSTALL_FM1_SOCKET_SUPPORT
#if INSTALL_FM1_SOCKET_SUPPORT == TRUE
#undef OPTION_FM1_SOCKET_SUPPORT
@@ -230,7 +229,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
#endif
#endif
-
#ifdef INSTALL_FP1_SOCKET_SUPPORT
#if INSTALL_FP1_SOCKET_SUPPORT == TRUE
#undef OPTION_FP1_SOCKET_SUPPORT
@@ -348,7 +346,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
#define OPTION_FAMILY15H FALSE
#endif
-
/* Check for invalid combinations of socket/family */
#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
#if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE)
@@ -386,7 +383,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
#endif
#endif
-
#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
#if (OPTION_FAMILY12H == FALSE)
#error No FM1 supported families included in the build
@@ -399,7 +395,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
#endif
#endif
-
#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
#if (OPTION_FAMILY12H == FALSE)
#error No FP1 supported families included in the build
@@ -1618,7 +1613,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
#endif
#endif
-
#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
#if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
#undef CFG_ACPI_PSTATES_PPC
@@ -2322,7 +2316,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
#define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
#else
- #define CFG_GNB_PCIE_SSID 0x12341022ul
+ #define CFG_GNB_PCIE_SSID 0x12341022
#endif
#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
@@ -2346,7 +2340,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
#define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
#else
- #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000ul
+ #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
#endif
#ifdef BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/agesa/f15tn/Include/PlatformMemoryConfiguration.h
index 094a3ae..2bd2637 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/PlatformMemoryConfiguration.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/PlatformMemoryConfiguration.h
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -38,6 +38,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
******************************************************************************
*/
@@ -70,7 +71,7 @@
///< DDR Speed Masks
///< Specifies the DDR Speed on a memory channel
///
-#define ANY_SPEED 0xFFFFFFFFul
+#define ANY_SPEED 0xFFFFFFFF
#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/f15tn/Legacy/PlatformMemoryConfiguration.inc
index 0f32cc6..3f65734 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/PlatformMemoryConfiguration.inc
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/PlatformMemoryConfiguration.inc
@@ -13,30 +13,31 @@
;
; ****************************************************************************
; *
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; * Copyright (C) 2012 Advanced Micro Devices, Inc.
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; * * Redistributions of source code must retain the above copyright
+; * notice, this list of conditions and the following disclaimer.
+; * * Redistributions in binary form must reproduce the above copyright
+; * notice, this list of conditions and the following disclaimer in the
+; * documentation and/or other materials provided with the distribution.
+; * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; * its contributors may be used to endorse or promote products derived
+; * from this software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
; *
; **************************************************************************
IFNDEF PSO_ENTRY
@@ -685,4 +686,4 @@ ENDM
; *
; * END OF TABLE DRIVEN OVERRIDE MACROS
; *
-; *****************************************************************************************
+; *****************************************************************************************
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c
index b307706..c7be476 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c
@@ -14,7 +14,7 @@
*/
/*****************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -38,6 +38,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
* ***************************************************************************
*/
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c
index 1df58aa..54b9d15 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c
@@ -19,7 +19,7 @@
*
******************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -43,6 +43,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
******************************************************************************
*/
@@ -454,7 +455,7 @@ excel331 (
{
AGESA_STATUS Status;
- Status = AmdAgesaCallout (0x00028146ul , (UINT32)SocketIdModuleId, MemData);
+ Status = AmdAgesaCallout (0x00028146, (UINT32)SocketIdModuleId, MemData);
return Status;
}
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/arch2008.asm b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/arch2008.asm
index a7be499..fe7cc6b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/arch2008.asm
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/arch2008.asm
@@ -7,30 +7,31 @@
;
;*****************************************************************************
;
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
;*****************************************************************************
.XLIST
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
index 7ed5f16..3de8aab 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
@@ -15,7 +15,7 @@
/*
******************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,6 +39,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
******************************************************************************
*/
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc
index be8ccf3..5743122 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc
@@ -13,30 +13,31 @@
;
; ****************************************************************************
; *
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; * Copyright (C) 2012 Advanced Micro Devices, Inc.
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; * * Redistributions of source code must retain the above copyright
+; * notice, this list of conditions and the following disclaimer.
+; * * Redistributions in binary form must reproduce the above copyright
+; * notice, this list of conditions and the following disclaimer in the
+; * documentation and/or other materials provided with the distribution.
+; * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; * its contributors may be used to endorse or promote products derived
+; * from this software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
; *
; **************************************************************************
diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
index a2c424a..3902372 100644
--- a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
@@ -15,7 +15,7 @@
/*
******************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,6 +39,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
******************************************************************************
*/
@@ -297,6 +298,7 @@ LibAmdReadCpuReg (
break;
default:
*Value = -1;
+ break;
}
}
VOID
@@ -325,7 +327,7 @@ LibAmdWriteCpuReg (
__writedr (7, Value);
break;
default:
- ;
+ break;
}
}
VOID
@@ -504,6 +506,7 @@ LibAmdIoRead (
break;
default:
ASSERT (FALSE);
+ break;
}
}
@@ -541,6 +544,7 @@ LibAmdIoWrite (
break;
default:
ASSERT (FALSE);
+ break;
}
}
@@ -641,6 +645,7 @@ LibAmdMemRead (
break;
default:
ASSERT (FALSE);
+ break;
}
}
@@ -679,6 +684,7 @@ LibAmdMemWrite (
break;
default:
ASSERT (FALSE);
+ break;
}
}
/*---------------------------------------------------------------------------------------*/
@@ -1297,6 +1303,7 @@ LibAmdGetDataFromPtr (
break;
default:
IDS_ERROR_TRAP;
+ break;
}
}
@@ -1336,6 +1343,7 @@ LibAmdAccessWidth (
default:
Width = 0;
IDS_ERROR_TRAP;
+ break;
}
return Width;
}
diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.h b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.h
index 1f14331..55f4310 100644
--- a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.h
+++ b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.h
@@ -15,7 +15,7 @@
/*
******************************************************************************
*
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,6 +39,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
******************************************************************************
**/
@@ -125,7 +126,8 @@ Write64Mem32 (
UINT64
ReadTSC (
- VOID);
+ VOID
+ );
// MSR
VOID
diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/x64/amdlib64.asm b/src/vendorcode/amd/agesa/f15tn/Lib/x64/amdlib64.asm
index c528a75..ab05991 100644
--- a/src/vendorcode/amd/agesa/f15tn/Lib/x64/amdlib64.asm
+++ b/src/vendorcode/amd/agesa/f15tn/Lib/x64/amdlib64.asm
@@ -12,30 +12,31 @@
; */
;*****************************************************************************
;
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
;*****************************************************************************
.code
diff --git a/src/vendorcode/amd/agesa/f15tn/cpcar.inc b/src/vendorcode/amd/agesa/f15tn/cpcar.inc
index 7d17e99..d487438 100644
--- a/src/vendorcode/amd/agesa/f15tn/cpcar.inc
+++ b/src/vendorcode/amd/agesa/f15tn/cpcar.inc
@@ -7,30 +7,31 @@
;
;*****************************************************************************
;
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
;*****************************************************************************
.LIST
.mmx
@@ -1341,7 +1342,6 @@ fam15_disable_stack_remote_read_exit:
_WRMSR
.endif
.endif
-
; Do Standard Family 15 work
mov ecx, HWCR ; MSR:C001_0015h
_RDMSR
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