[coreboot-gerrit] New patch to review for coreboot: 3430956 model_6ex: Determine CPU_ADDR_BITS dynamically

[Vladimir Serbinenko (phcoder@gmail.com)]

Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7481

-gerrit

commit 34309563d92b9d9af2b6d39da50fb29cd2d6add8
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date:   Sun Nov 16 20:08:32 2014 +0100

    model_6ex: Determine CPU_ADDR_BITS dynamically
    
    Change-Id: I4cc46b1fd5be1350ef92fb116eaf0bbc7b7caf8c
    Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
 src/arch/x86/lib/cpu_addr_size.S         | 25 +++++++++++++++++++++++++
 src/cpu/intel/model_6ex/cache_as_ram.inc | 32 ++++++++++++++++++++++++++------
 2 files changed, 51 insertions(+), 6 deletions(-)

diff --git a/src/arch/x86/lib/cpu_addr_size.S b/src/arch/x86/lib/cpu_addr_size.S
new file mode 100644
index 0000000..31ad420
--- /dev/null
+++ b/src/arch/x86/lib/cpu_addr_size.S
@@ -0,0 +1,25 @@
+	/* Sets %bl to the number of cpu phys its minus 32.  */
+#define CPUID_FEATURE_PAE (1 << 6)
+#define CPUID_FEATURE_PSE36 (1 << 17)
+
+	movl $0x80000000, %eax
+	cpuid
+	cmp $0x80000008, %eax
+	jb 1f
+	movl $0x80000008, %eax
+	cpuid
+	subb $32, %al
+	movb %al, %bl
+	jmp 3f
+
+1:
+	movl $1, %eax
+	cpuid
+	testl $(CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36), %edx
+	jnz 2f
+	xorb %bl, %bl
+	jmp 3f
+2:
+	movb $4, %bl
+3:
+	xorb %bl, %bl
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 09b8e93..7fe364b 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -22,8 +22,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
 
-#define CPU_PHYSMASK_HI  (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
-
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
@@ -63,10 +61,17 @@ clear_mtrrs:
 	xorl	%edx, %edx
 	wrmsr
 
+#include <arch/x86/lib/cpu_addr_size.S>
+
 	/* Set Cache-as-RAM mask. */
+	movb	%bl, %cl
+	xorl	%eax, %eax
+	incl	%eax
+	shll	%cl, %eax
+	decl	%eax
+	movl	%eax, %edx
 	movl	$(MTRRphysMask_MSR(0)), %ecx
 	movl	$(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
-	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
 
 	/* Enable MTRR. */
@@ -113,8 +118,13 @@ clear_mtrrs:
 	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr
 
+	movb	%bl, %cl
+	xorl	%eax, %eax
+	incl	%eax
+	shll	%cl, %eax
+	decl	%eax
+	movl	%eax, %edx
 	movl	$MTRRphysMask_MSR(1), %ecx
-	movl	$CPU_PHYSMASK_HI, %edx
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE */
@@ -180,9 +190,14 @@ clear_mtrrs:
 	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
 	xorl	%edx, %edx
 	wrmsr
+	movb	%bl, %cl
+	xorl	%eax, %eax
+	incl	%eax
+	shll	%cl, %eax
+	decl	%eax
+	movl	%eax, %edx
 	movl	$MTRRphysMask_MSR(0), %ecx
 	movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
-	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
 
 #if CACHE_ROM_SIZE
@@ -191,9 +206,14 @@ clear_mtrrs:
 	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
 	xorl	%edx, %edx
 	wrmsr
+	movb	%bl, %cl
+	xorl	%eax, %eax
+	incl	%eax
+	shll	%cl, %eax
+	decl	%eax
+	movl	%eax, %edx
 	movl	$MTRRphysMask_MSR(1), %ecx
 	movl	$(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
-	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
 #endif