[coreboot-gerrit] Patch set updated for coreboot: e22ac36 nyan: tpm: Increase the TPM frequency to 400 KHz.

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7461

-gerrit

commit e22ac362f06bc7b2459adb61641dc5e93f4f9156
Author: Gabe Black <gabeblack at google.com>
Date:   Wed Mar 26 21:58:06 2014 -0700

    nyan: tpm: Increase the TPM frequency to 400 KHz.
    
    The TPM now works correctly with the I2C bus running at 400 KHz. Running it at
    that frequency saves some boot time.
    
    CQ-DEPEND=CL:191634
    CQ-DEPEND=CL:191793
    BUG=chrome-os-partner:27220
    TEST=Built and booted on nyan with and without EFS.
    BRANCH=None
    
    Original-Change-Id: I157308c2745342dc1ada4499433004c7ce1c6435
    Original-Signed-off-by: Gabe Black <gabeblack at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/191813
    Original-Reviewed-by: Tom Warren <twarren at nvidia.com>
    Original-Reviewed-by: Jimmy Zhang <jimmzhang at nvidia.com>
    Original-Reviewed-by: Gabe Black <gabeblack at chromium.org>
    Original-Tested-by: Gabe Black <gabeblack at chromium.org>
    (cherry picked from commit 39a740d488d8f33ee698805bc2a8438263162cc8)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I02978407e20cc9d526545157a3a3304729a91010
---
 src/mainboard/google/nyan/romstage.c       | 7 +------
 src/mainboard/google/nyan_big/romstage.c   | 7 +------
 src/mainboard/google/nyan_blaze/romstage.c | 7 +------
 3 files changed, 3 insertions(+), 18 deletions(-)

diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index ee54a50..eeec9bd 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -134,12 +134,7 @@ static void configure_ec_spi_bus(void)
 
 static void configure_tpm_i2c_bus(void)
 {
-	/*
-	 * The TPM is on I2C3 and can theoretically run at 400 KHz but doesn't
-	 * seem to work above around 40 KHz. It's set to run at 100 KHz in the
-	 * kernel.
-	 */
-	clock_configure_i2c_scl_freq(i2c3, PLLP, 40);
+	clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
 
 	i2c_init(2);
 }
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index e1597c8..6327c97 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -134,12 +134,7 @@ static void configure_ec_spi_bus(void)
 
 static void configure_tpm_i2c_bus(void)
 {
-	/*
-	 * The TPM is on I2C3 and can theoretically run at 400 KHz but doesn't
-	 * seem to work above around 40 KHz. It's set to run at 100 KHz in the
-	 * kernel.
-	 */
-	clock_configure_i2c_scl_freq(i2c3, PLLP, 40);
+	clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
 
 	i2c_init(2);
 }
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c
index e1597c8..6327c97 100644
--- a/src/mainboard/google/nyan_blaze/romstage.c
+++ b/src/mainboard/google/nyan_blaze/romstage.c
@@ -134,12 +134,7 @@ static void configure_ec_spi_bus(void)
 
 static void configure_tpm_i2c_bus(void)
 {
-	/*
-	 * The TPM is on I2C3 and can theoretically run at 400 KHz but doesn't
-	 * seem to work above around 40 KHz. It's set to run at 100 KHz in the
-	 * kernel.
-	 */
-	clock_configure_i2c_scl_freq(i2c3, PLLP, 40);
+	clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
 
 	i2c_init(2);
 }