[coreboot-gerrit] Patch set updated for coreboot: 82d7221 nyan: big: Check dram_end when setting up caching in ROM stage.

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7405

-gerrit

commit 82d7221d58e538b85f9bac63171aea75e2ccd3eb
Author: Gabe Black <gabeblack at google.com>
Date:   Sat Feb 15 00:05:03 2014 -0800

    nyan: big: Check dram_end when setting up caching in ROM stage.
    
    When setting up caching on nyan and big, we would set the region after DRAM to
    the end of the address space as uncachable. DRAM may actually extend beyond
    the end of the address space, so that may result in address aliasing or other
    problems. This change adds a check to make sure there's actually space there.
    
    BUG=None
    TEST=Built for big.
    BRANCH=None
    
    Original-Change-Id: Ic0a98550222f9dfc0aeafd67a2dd1c0c8f4ece44
    Original-Signed-off-by: Gabe Black <gabeblack at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/186769
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Original-Commit-Queue: Gabe Black <gabeblack at chromium.org>
    Original-Tested-by: Gabe Black <gabeblack at chromium.org>
    (cherry picked from commit 1866a4d2a001beb97779b611b8b69c63175048f4)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: If1ca8b5bd4efab8962e03c0d9eaa70c0327ea6b5
---
 src/mainboard/google/nyan/romstage.c     | 3 ++-
 src/mainboard/google/nyan_big/romstage.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index 7fb9570..28827c8 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -93,7 +93,8 @@ static void __attribute__((noinline)) romstage(void)
 	mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
 	mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
 			 CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
-	mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
+	if (dram_end < 4096)
+		mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
 	mmu_disable_range(0, 1);
 	dcache_mmu_enable();
 
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index c18138a..0fbe316 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -93,7 +93,8 @@ static void __attribute__((noinline)) romstage(void)
 	mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
 	mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
 			 CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
-	mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
+	if (dram_end < 4096)
+		mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
 	mmu_disable_range(0, 1);
 	dcache_mmu_enable();