[coreboot-gerrit] Patch set updated for coreboot: a3d1638 spd_cache debug: Log invalid CRC checksum

[Tobias Diedrich (ranma+coreboot@tdiedrich.de)]

Tobias Diedrich (ranma+coreboot at tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7393

-gerrit

commit a3d1638ce2b32f20e00c69d37898046ff45bc302
Author: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Date:   Mon Nov 10 22:21:58 2014 +0100

    spd_cache debug: Log invalid CRC checksum
    
    "SPD has a invalid or zero-valued CRC" is not a very useful message,
    so show the actual and expected values.
    
    Change-Id: I31a1cdacc82240c699627769d490b94f5d378e86
    Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
---
 src/device/dram/spd_cache.c               | 3 ++-
 src/northbridge/amd/agesa/common/common.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c
index 0032f32..f19e128 100644
--- a/src/device/dram/spd_cache.c
+++ b/src/device/dram/spd_cache.c
@@ -52,7 +52,8 @@ int read_spd_from_cbfs(u8 *buf, int idx)
 	if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0))
 	 || (buf[SPD_CRC_LO] != (crc & 0xff))
 	 || (buf[SPD_CRC_HI] != (crc >> 8))) {
-		printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n");
+		printk(BIOS_WARNING, "SPD crc %02x%02x is invalid, should be %04x\n",
+			buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc);
 		buf[SPD_CRC_LO] = crc & 0xff;
 		buf[SPD_CRC_HI] = crc >> 8;
 		u16 i;
diff --git a/src/northbridge/amd/agesa/common/common.c b/src/northbridge/amd/agesa/common/common.c
index 91c58e3..eb2698e 100644
--- a/src/northbridge/amd/agesa/common/common.c
+++ b/src/northbridge/amd/agesa/common/common.c
@@ -64,7 +64,8 @@ AGESA_STATUS common_ReadCbfsSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 	if (((info->Buffer[SPD_CRC_LO] == 0) && (info->Buffer[SPD_CRC_HI] == 0))
 	  || (info->Buffer[SPD_CRC_LO] != (crc & 0xff))
 	  || (info->Buffer[SPD_CRC_HI] != (crc >> 8))) {
-		printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n");
+		printk(BIOS_WARNING, "SPD crc %02x%02x is invalid, should be %04x\n",
+			info->Buffer[SPD_CRC_HI], info->Buffer[SPD_CRC_LO], crc);
 		info->Buffer[SPD_CRC_LO] = crc & 0xff;
 		info->Buffer[SPD_CRC_HI] = crc >> 8;
 		u16 i;