[coreboot-gerrit] Patch set updated for coreboot: 351c05c superio/fintek/f81216h: Implement device support
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Sat Nov 1 08:16:40 CET 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7309
-gerrit
commit 351c05c8a5fba536f2900362ed7964ec8ddc31b9
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Sat Nov 1 10:19:58 2014 +1100
superio/fintek/f81216h: Implement device support
Change-Id: I20a34b569f109dd12af29e9e0cee8f7f6b8ebb80
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/superio/fintek/Kconfig | 4 +
src/superio/fintek/Makefile.inc | 1 +
src/superio/fintek/f81216h/Makefile.inc | 22 ++++++
src/superio/fintek/f81216h/chip.h | 40 ++++++++++
src/superio/fintek/f81216h/early_serial.c | 68 +++++++++++++++++
src/superio/fintek/f81216h/f81216h.h | 46 ++++++++++++
src/superio/fintek/f81216h/superio.c | 119 ++++++++++++++++++++++++++++++
7 files changed, 300 insertions(+)
diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig
index f577898..e9cbe74 100644
--- a/src/superio/fintek/Kconfig
+++ b/src/superio/fintek/Kconfig
@@ -47,6 +47,10 @@ config SUPERIO_FINTEK_F71889
bool
select SUPERIO_FINTEK_COMMON_ROMSTAGE
+config SUPERIO_FINTEK_F81216H
+ bool
+# N.B. 'special romstage'
+
config SUPERIO_FINTEK_F81865F
bool
select SUPERIO_FINTEK_COMMON_ROMSTAGE
diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc
index 1b11336..5756393 100644
--- a/src/superio/fintek/Makefile.inc
+++ b/src/superio/fintek/Makefile.inc
@@ -26,4 +26,5 @@ subdirs-y += f71863fg
subdirs-y += f71869ad
subdirs-y += f71872
subdirs-y += f71889
+subdirs-y += f81216h
subdirs-y += f81865f
diff --git a/src/superio/fintek/f81216h/Makefile.inc b/src/superio/fintek/f81216h/Makefile.inc
new file mode 100644
index 0000000..f473ef2
--- /dev/null
+++ b/src/superio/fintek/f81216h/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+romstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += early_serial.c
+ramstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += superio.c
diff --git a/src/superio/fintek/f81216h/chip.h b/src/superio/fintek/f81216h/chip.h
new file mode 100644
index 0000000..9b54ce1
--- /dev/null
+++ b/src/superio/fintek/f81216h/chip.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_FINTEK_F81216H_CHIP_H
+#define SUPERIO_FINTEK_F81216H_CHIP_H
+
+#include <stdint.h>
+
+/* Member variables are defined in devicetree.cb. */
+struct superio_fintek_f81216h_config {
+ /**
+ * KEY1 KEY0 Enter key
+ * 0 0 0x77 (default)
+ * 0 1 0xA0
+ * 1 0 0x87
+ * 1 1 0x67
+ *
+ * See page 17 of data sheet.
+ */
+ uint8_t conf_key_mode;
+};
+
+#endif /* SUPERIO_FINTEK_F81216H_CHIP_H */
diff --git a/src/superio/fintek/f81216h/early_serial.c b/src/superio/fintek/f81216h/early_serial.c
new file mode 100644
index 0000000..6b667df
--- /dev/null
+++ b/src/superio/fintek/f81216h/early_serial.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
+#include "fintek.h"
+
+static u8 f81216h_entry_key;
+#define FINTEK_EXIT_KEY 0xAA
+
+static void pnp_enter_conf_state(pnp_devfn_t dev)
+{
+ u16 port = dev >> 8;
+ outb(f81216h_entry_key, port);
+ outb(f81216h_entry_key, port);
+}
+
+static void pnp_exit_conf_state(pnp_devfn_t dev)
+{
+ u16 port = dev >> 8;
+ outb(FINTEK_EXIT_KEY, port);
+}
+
+/* Bring up early serial debugging output before the RAM is initialized. */
+void f81216h_enable_serial(pnp_devfn_t dev, u16 iobase, enum mode_key k)
+{
+ switch(k) {
+ MODE_6767:
+ f81216h_entry_key = 0x67;
+ break;
+ MODE_7777:
+ f81216h_entry_key = 0x77;
+ break;
+ MODE_8787:
+ f81216h_entry_key = 0x87;
+ break;
+ MODE_A0A0:
+ f81216h_entry_key = 0xa0;
+ break;
+ default:
+ f81216h_entry_key = 0x77; /* (safe to be hw default) */
+ }
+
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
diff --git a/src/superio/fintek/f81216h/f81216h.h b/src/superio/fintek/f81216h/f81216h.h
new file mode 100644
index 0000000..37e7753
--- /dev/null
+++ b/src/superio/fintek/f81216h/f81216h.h
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_FINTEK_F81216H_H
+#define SUPERIO_FINTEK_F81216H_H
+
+/* Logical Device Numbers (LDN). */
+#define F81216H_SP1 0x00 /* UART1 (+CIR mode) */
+#define F81216H_SP2 0x01 /* UART2 */
+#define F81216H_SP3 0x02 /* UART3 */
+#define F81216H_SP4 0x03 /* UART4 */
+#define F81216H_WDT 0x08 /* WDT */
+
+/**
+ * The PNP config entry key is parameterised
+ * by two bits on this Super I/O with 0x77 as
+ * the default key.
+ * See page 17 of data sheet for details.
+ */
+enum {
+ MODE_6767,
+ MODE_7777,
+ MODE_8787,
+ MODE_A0A0,
+} mode_key;
+
+void f81216h_enable_serial(pnp_devfn_t dev, u16 iobase, enum mode_key k);
+
+#endif /* SUPERIO_FINTEK_F81216H_H */
diff --git a/src/superio/fintek/f81216h/superio.c b/src/superio/fintek/f81216h/superio.c
new file mode 100644
index 0000000..eed165a
--- /dev/null
+++ b/src/superio/fintek/f81216h/superio.c
@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <superio/conf_mode.h>
+#include <console/console.h>
+#include <stdlib.h>
+
+#include "chip.h"
+#include "f81216h.h"
+
+
+static void pnp_enter_ext_func_mode(struct device *dev)
+{
+ const struct superio_fintek_f81216h_config *conf = dev->chip_info;
+
+ u8 key;
+
+ /**
+ * KEY1 KEY0 Enter key
+ * 0 0 0x77 (default)
+ * 0 1 0xA0
+ * 1 0 0x87
+ * 1 1 0x67
+ *
+ * See page 17 of data sheet.
+ */
+ switch(conf->conf_key_mode) {
+ case 0:
+ key = 0x77; /* (default) */
+ break;
+ case 1:
+ key = 0xa0;
+ break;
+ case 2:
+ key = 0x87;
+ break;
+ case 3:
+ key = 0x67;
+ break;
+ default:
+ key = 0x77; /* safe to be hw default */
+ }
+
+ outb(key, dev->path.pnp.port);
+ outb(key, dev->path.pnp.port);
+}
+
+static void pnp_exit_ext_func_mode(struct device *dev)
+{
+ outb(0xaa, dev->path.pnp.port);
+}
+
+static const struct pnp_mode_ops pnp_conf_mode_ops = {
+ .enter_conf_mode = pnp_enter_ext_func_mode,
+ .exit_conf_mode = pnp_exit_ext_func_mode,
+};
+
+
+static void f81216h_init(struct device *dev)
+{
+ if (!dev->enabled)
+ return;
+
+ switch(dev->path.pnp.device) {
+ case F81216H_SP1:
+ case F81216H_SP2:
+ case F81216H_SP3:
+ case F81216H_SP4:
+ case F81216H_WDT:
+ break;
+ }
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = f81216h_init,
+ .ops_pnp_mode = &pnp_conf_mode_ops,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, F81216H_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, F81216H_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, F81216H_SP3, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, F81216H_SP4, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, F81216H_WDT, },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_fintek_f81216h_ops = {
+ CHIP_NAME("Fintek F81216H/D/DG/F/FG Super I/O")
+ .enable_dev = enable_dev
+};
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